forked from OSchip/llvm-project
851 lines
28 KiB
C++
851 lines
28 KiB
C++
//===-- X86AsmBackend.cpp - X86 Assembler Backend -------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/X86BaseInfo.h"
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#include "MCTargetDesc/X86FixupKinds.h"
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#include "llvm/ADT/StringSwitch.h"
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#include "llvm/MC/MCAsmBackend.h"
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#include "llvm/MC/MCELFObjectWriter.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCFixupKindInfo.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCMachObjectWriter.h"
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#include "llvm/MC/MCObjectWriter.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCSectionCOFF.h"
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#include "llvm/MC/MCSectionELF.h"
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#include "llvm/MC/MCSectionMachO.h"
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#include "llvm/Support/ELF.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/MachO.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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static unsigned getFixupKindLog2Size(unsigned Kind) {
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switch (Kind) {
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default:
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llvm_unreachable("invalid fixup kind!");
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case FK_PCRel_1:
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case FK_SecRel_1:
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case FK_Data_1:
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return 0;
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case FK_PCRel_2:
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case FK_SecRel_2:
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case FK_Data_2:
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return 1;
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case FK_PCRel_4:
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case X86::reloc_riprel_4byte:
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case X86::reloc_riprel_4byte_relax:
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case X86::reloc_riprel_4byte_relax_rex:
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case X86::reloc_riprel_4byte_movq_load:
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case X86::reloc_signed_4byte:
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case X86::reloc_global_offset_table:
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case FK_SecRel_4:
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case FK_Data_4:
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return 2;
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case FK_PCRel_8:
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case FK_SecRel_8:
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case FK_Data_8:
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case X86::reloc_global_offset_table8:
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return 3;
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}
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}
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namespace {
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class X86ELFObjectWriter : public MCELFObjectTargetWriter {
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public:
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X86ELFObjectWriter(bool is64Bit, uint8_t OSABI, uint16_t EMachine,
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bool HasRelocationAddend, bool foobar)
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: MCELFObjectTargetWriter(is64Bit, OSABI, EMachine, HasRelocationAddend) {}
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};
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class X86AsmBackend : public MCAsmBackend {
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const StringRef CPU;
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bool HasNopl;
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const uint64_t MaxNopLength;
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public:
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X86AsmBackend(const Target &T, StringRef CPU)
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: MCAsmBackend(), CPU(CPU),
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MaxNopLength((CPU == "slm" || CPU == "lakemont") ? 7 : 15) {
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HasNopl = CPU != "generic" && CPU != "i386" && CPU != "i486" &&
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CPU != "i586" && CPU != "pentium" && CPU != "pentium-mmx" &&
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CPU != "i686" && CPU != "k6" && CPU != "k6-2" && CPU != "k6-3" &&
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CPU != "geode" && CPU != "winchip-c6" && CPU != "winchip2" &&
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CPU != "c3" && CPU != "c3-2";
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}
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unsigned getNumFixupKinds() const override {
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return X86::NumTargetFixupKinds;
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}
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const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override {
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const static MCFixupKindInfo Infos[X86::NumTargetFixupKinds] = {
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{"reloc_riprel_4byte", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
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{"reloc_riprel_4byte_movq_load", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
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{"reloc_riprel_4byte_relax", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
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{"reloc_riprel_4byte_relax_rex", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
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{"reloc_signed_4byte", 0, 32, 0},
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{"reloc_global_offset_table", 0, 32, 0},
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{"reloc_global_offset_table8", 0, 64, 0},
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};
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if (Kind < FirstTargetFixupKind)
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return MCAsmBackend::getFixupKindInfo(Kind);
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assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
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"Invalid kind!");
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return Infos[Kind - FirstTargetFixupKind];
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}
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void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
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uint64_t Value, bool IsPCRel) const override {
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unsigned Size = 1 << getFixupKindLog2Size(Fixup.getKind());
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assert(Fixup.getOffset() + Size <= DataSize &&
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"Invalid fixup offset!");
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// Check that uppper bits are either all zeros or all ones.
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// Specifically ignore overflow/underflow as long as the leakage is
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// limited to the lower bits. This is to remain compatible with
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// other assemblers.
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assert(isIntN(Size * 8 + 1, Value) &&
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"Value does not fit in the Fixup field");
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for (unsigned i = 0; i != Size; ++i)
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Data[Fixup.getOffset() + i] = uint8_t(Value >> (i * 8));
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}
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bool mayNeedRelaxation(const MCInst &Inst) const override;
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bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
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const MCRelaxableFragment *DF,
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const MCAsmLayout &Layout) const override;
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void relaxInstruction(const MCInst &Inst, MCInst &Res) const override;
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bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override;
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};
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} // end anonymous namespace
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static unsigned getRelaxedOpcodeBranch(unsigned Op) {
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switch (Op) {
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default:
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return Op;
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case X86::JAE_1: return X86::JAE_4;
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case X86::JA_1: return X86::JA_4;
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case X86::JBE_1: return X86::JBE_4;
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case X86::JB_1: return X86::JB_4;
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case X86::JE_1: return X86::JE_4;
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case X86::JGE_1: return X86::JGE_4;
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case X86::JG_1: return X86::JG_4;
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case X86::JLE_1: return X86::JLE_4;
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case X86::JL_1: return X86::JL_4;
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case X86::JMP_1: return X86::JMP_4;
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case X86::JNE_1: return X86::JNE_4;
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case X86::JNO_1: return X86::JNO_4;
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case X86::JNP_1: return X86::JNP_4;
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case X86::JNS_1: return X86::JNS_4;
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case X86::JO_1: return X86::JO_4;
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case X86::JP_1: return X86::JP_4;
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case X86::JS_1: return X86::JS_4;
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}
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}
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static unsigned getRelaxedOpcodeArith(unsigned Op) {
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switch (Op) {
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default:
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return Op;
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// IMUL
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case X86::IMUL16rri8: return X86::IMUL16rri;
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case X86::IMUL16rmi8: return X86::IMUL16rmi;
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case X86::IMUL32rri8: return X86::IMUL32rri;
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case X86::IMUL32rmi8: return X86::IMUL32rmi;
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case X86::IMUL64rri8: return X86::IMUL64rri32;
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case X86::IMUL64rmi8: return X86::IMUL64rmi32;
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// AND
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case X86::AND16ri8: return X86::AND16ri;
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case X86::AND16mi8: return X86::AND16mi;
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case X86::AND32ri8: return X86::AND32ri;
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case X86::AND32mi8: return X86::AND32mi;
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case X86::AND64ri8: return X86::AND64ri32;
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case X86::AND64mi8: return X86::AND64mi32;
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// OR
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case X86::OR16ri8: return X86::OR16ri;
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case X86::OR16mi8: return X86::OR16mi;
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case X86::OR32ri8: return X86::OR32ri;
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case X86::OR32mi8: return X86::OR32mi;
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case X86::OR64ri8: return X86::OR64ri32;
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case X86::OR64mi8: return X86::OR64mi32;
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// XOR
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case X86::XOR16ri8: return X86::XOR16ri;
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case X86::XOR16mi8: return X86::XOR16mi;
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case X86::XOR32ri8: return X86::XOR32ri;
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case X86::XOR32mi8: return X86::XOR32mi;
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case X86::XOR64ri8: return X86::XOR64ri32;
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case X86::XOR64mi8: return X86::XOR64mi32;
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// ADD
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case X86::ADD16ri8: return X86::ADD16ri;
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case X86::ADD16mi8: return X86::ADD16mi;
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case X86::ADD32ri8: return X86::ADD32ri;
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case X86::ADD32mi8: return X86::ADD32mi;
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case X86::ADD64ri8: return X86::ADD64ri32;
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case X86::ADD64mi8: return X86::ADD64mi32;
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// ADC
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case X86::ADC16ri8: return X86::ADC16ri;
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case X86::ADC16mi8: return X86::ADC16mi;
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case X86::ADC32ri8: return X86::ADC32ri;
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case X86::ADC32mi8: return X86::ADC32mi;
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case X86::ADC64ri8: return X86::ADC64ri32;
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case X86::ADC64mi8: return X86::ADC64mi32;
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// SUB
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case X86::SUB16ri8: return X86::SUB16ri;
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case X86::SUB16mi8: return X86::SUB16mi;
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case X86::SUB32ri8: return X86::SUB32ri;
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case X86::SUB32mi8: return X86::SUB32mi;
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case X86::SUB64ri8: return X86::SUB64ri32;
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case X86::SUB64mi8: return X86::SUB64mi32;
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// SBB
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case X86::SBB16ri8: return X86::SBB16ri;
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case X86::SBB16mi8: return X86::SBB16mi;
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case X86::SBB32ri8: return X86::SBB32ri;
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case X86::SBB32mi8: return X86::SBB32mi;
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case X86::SBB64ri8: return X86::SBB64ri32;
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case X86::SBB64mi8: return X86::SBB64mi32;
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// CMP
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case X86::CMP16ri8: return X86::CMP16ri;
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case X86::CMP16mi8: return X86::CMP16mi;
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case X86::CMP32ri8: return X86::CMP32ri;
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case X86::CMP32mi8: return X86::CMP32mi;
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case X86::CMP64ri8: return X86::CMP64ri32;
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case X86::CMP64mi8: return X86::CMP64mi32;
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// PUSH
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case X86::PUSH32i8: return X86::PUSHi32;
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case X86::PUSH16i8: return X86::PUSHi16;
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case X86::PUSH64i8: return X86::PUSH64i32;
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}
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}
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static unsigned getRelaxedOpcode(unsigned Op) {
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unsigned R = getRelaxedOpcodeArith(Op);
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if (R != Op)
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return R;
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return getRelaxedOpcodeBranch(Op);
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}
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bool X86AsmBackend::mayNeedRelaxation(const MCInst &Inst) const {
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// Branches can always be relaxed.
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if (getRelaxedOpcodeBranch(Inst.getOpcode()) != Inst.getOpcode())
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return true;
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// Check if this instruction is ever relaxable.
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if (getRelaxedOpcodeArith(Inst.getOpcode()) == Inst.getOpcode())
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return false;
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// Check if the relaxable operand has an expression. For the current set of
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// relaxable instructions, the relaxable operand is always the last operand.
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unsigned RelaxableOp = Inst.getNumOperands() - 1;
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if (Inst.getOperand(RelaxableOp).isExpr())
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return true;
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return false;
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}
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bool X86AsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup,
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uint64_t Value,
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const MCRelaxableFragment *DF,
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const MCAsmLayout &Layout) const {
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// Relax if the value is too big for a (signed) i8.
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return int64_t(Value) != int64_t(int8_t(Value));
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}
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// FIXME: Can tblgen help at all here to verify there aren't other instructions
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// we can relax?
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void X86AsmBackend::relaxInstruction(const MCInst &Inst, MCInst &Res) const {
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// The only relaxations X86 does is from a 1byte pcrel to a 4byte pcrel.
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unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode());
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if (RelaxedOp == Inst.getOpcode()) {
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SmallString<256> Tmp;
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raw_svector_ostream OS(Tmp);
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Inst.dump_pretty(OS);
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OS << "\n";
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report_fatal_error("unexpected instruction to relax: " + OS.str());
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}
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Res = Inst;
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Res.setOpcode(RelaxedOp);
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}
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/// \brief Write a sequence of optimal nops to the output, covering \p Count
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/// bytes.
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/// \return - true on success, false on failure
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bool X86AsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
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static const uint8_t Nops[10][10] = {
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// nop
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{0x90},
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// xchg %ax,%ax
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{0x66, 0x90},
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// nopl (%[re]ax)
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{0x0f, 0x1f, 0x00},
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// nopl 0(%[re]ax)
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{0x0f, 0x1f, 0x40, 0x00},
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// nopl 0(%[re]ax,%[re]ax,1)
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{0x0f, 0x1f, 0x44, 0x00, 0x00},
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// nopw 0(%[re]ax,%[re]ax,1)
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{0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00},
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// nopl 0L(%[re]ax)
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{0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00},
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// nopl 0L(%[re]ax,%[re]ax,1)
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{0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
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// nopw 0L(%[re]ax,%[re]ax,1)
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{0x66, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
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// nopw %cs:0L(%[re]ax,%[re]ax,1)
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{0x66, 0x2e, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
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};
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// This CPU doesn't support long nops. If needed add more.
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// FIXME: Can we get this from the subtarget somehow?
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// FIXME: We could generated something better than plain 0x90.
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if (!HasNopl) {
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for (uint64_t i = 0; i < Count; ++i)
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OW->write8(0x90);
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return true;
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}
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// 15 is the longest single nop instruction. Emit as many 15-byte nops as
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// needed, then emit a nop of the remaining length.
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do {
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const uint8_t ThisNopLength = (uint8_t) std::min(Count, MaxNopLength);
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const uint8_t Prefixes = ThisNopLength <= 10 ? 0 : ThisNopLength - 10;
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for (uint8_t i = 0; i < Prefixes; i++)
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OW->write8(0x66);
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const uint8_t Rest = ThisNopLength - Prefixes;
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for (uint8_t i = 0; i < Rest; i++)
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OW->write8(Nops[Rest - 1][i]);
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Count -= ThisNopLength;
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} while (Count != 0);
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return true;
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}
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/* *** */
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namespace {
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class ELFX86AsmBackend : public X86AsmBackend {
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public:
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uint8_t OSABI;
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ELFX86AsmBackend(const Target &T, uint8_t OSABI, StringRef CPU)
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: X86AsmBackend(T, CPU), OSABI(OSABI) {}
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};
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class ELFX86_32AsmBackend : public ELFX86AsmBackend {
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public:
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ELFX86_32AsmBackend(const Target &T, uint8_t OSABI, StringRef CPU)
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: ELFX86AsmBackend(T, OSABI, CPU) {}
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MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
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return createX86ELFObjectWriter(OS, /*IsELF64*/ false, OSABI, ELF::EM_386);
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}
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};
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class ELFX86_X32AsmBackend : public ELFX86AsmBackend {
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public:
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ELFX86_X32AsmBackend(const Target &T, uint8_t OSABI, StringRef CPU)
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: ELFX86AsmBackend(T, OSABI, CPU) {}
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MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
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return createX86ELFObjectWriter(OS, /*IsELF64*/ false, OSABI,
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ELF::EM_X86_64);
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}
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};
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class ELFX86_IAMCUAsmBackend : public ELFX86AsmBackend {
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public:
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ELFX86_IAMCUAsmBackend(const Target &T, uint8_t OSABI, StringRef CPU)
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: ELFX86AsmBackend(T, OSABI, CPU) {}
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MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
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return createX86ELFObjectWriter(OS, /*IsELF64*/ false, OSABI,
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ELF::EM_IAMCU);
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}
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};
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class ELFX86_64AsmBackend : public ELFX86AsmBackend {
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public:
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ELFX86_64AsmBackend(const Target &T, uint8_t OSABI, StringRef CPU)
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: ELFX86AsmBackend(T, OSABI, CPU) {}
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MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
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return createX86ELFObjectWriter(OS, /*IsELF64*/ true, OSABI, ELF::EM_X86_64);
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}
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};
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class WindowsX86AsmBackend : public X86AsmBackend {
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bool Is64Bit;
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public:
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WindowsX86AsmBackend(const Target &T, bool is64Bit, StringRef CPU)
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: X86AsmBackend(T, CPU)
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, Is64Bit(is64Bit) {
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}
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Optional<MCFixupKind> getFixupKind(StringRef Name) const override {
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return StringSwitch<Optional<MCFixupKind>>(Name)
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.Case("dir32", FK_Data_4)
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.Case("secrel32", FK_SecRel_4)
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.Case("secidx", FK_SecRel_2)
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.Default(MCAsmBackend::getFixupKind(Name));
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}
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MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
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return createX86WinCOFFObjectWriter(OS, Is64Bit);
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}
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};
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namespace CU {
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/// Compact unwind encoding values.
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|
enum CompactUnwindEncodings {
|
|
/// [RE]BP based frame where [RE]BP is pused on the stack immediately after
|
|
/// the return address, then [RE]SP is moved to [RE]BP.
|
|
UNWIND_MODE_BP_FRAME = 0x01000000,
|
|
|
|
/// A frameless function with a small constant stack size.
|
|
UNWIND_MODE_STACK_IMMD = 0x02000000,
|
|
|
|
/// A frameless function with a large constant stack size.
|
|
UNWIND_MODE_STACK_IND = 0x03000000,
|
|
|
|
/// No compact unwind encoding is available.
|
|
UNWIND_MODE_DWARF = 0x04000000,
|
|
|
|
/// Mask for encoding the frame registers.
|
|
UNWIND_BP_FRAME_REGISTERS = 0x00007FFF,
|
|
|
|
/// Mask for encoding the frameless registers.
|
|
UNWIND_FRAMELESS_STACK_REG_PERMUTATION = 0x000003FF
|
|
};
|
|
|
|
} // end CU namespace
|
|
|
|
class DarwinX86AsmBackend : public X86AsmBackend {
|
|
const MCRegisterInfo &MRI;
|
|
|
|
/// \brief Number of registers that can be saved in a compact unwind encoding.
|
|
enum { CU_NUM_SAVED_REGS = 6 };
|
|
|
|
mutable unsigned SavedRegs[CU_NUM_SAVED_REGS];
|
|
bool Is64Bit;
|
|
|
|
unsigned OffsetSize; ///< Offset of a "push" instruction.
|
|
unsigned MoveInstrSize; ///< Size of a "move" instruction.
|
|
unsigned StackDivide; ///< Amount to adjust stack size by.
|
|
protected:
|
|
/// \brief Size of a "push" instruction for the given register.
|
|
unsigned PushInstrSize(unsigned Reg) const {
|
|
switch (Reg) {
|
|
case X86::EBX:
|
|
case X86::ECX:
|
|
case X86::EDX:
|
|
case X86::EDI:
|
|
case X86::ESI:
|
|
case X86::EBP:
|
|
case X86::RBX:
|
|
case X86::RBP:
|
|
return 1;
|
|
case X86::R12:
|
|
case X86::R13:
|
|
case X86::R14:
|
|
case X86::R15:
|
|
return 2;
|
|
}
|
|
return 1;
|
|
}
|
|
|
|
/// \brief Implementation of algorithm to generate the compact unwind encoding
|
|
/// for the CFI instructions.
|
|
uint32_t
|
|
generateCompactUnwindEncodingImpl(ArrayRef<MCCFIInstruction> Instrs) const {
|
|
if (Instrs.empty()) return 0;
|
|
|
|
// Reset the saved registers.
|
|
unsigned SavedRegIdx = 0;
|
|
memset(SavedRegs, 0, sizeof(SavedRegs));
|
|
|
|
bool HasFP = false;
|
|
|
|
// Encode that we are using EBP/RBP as the frame pointer.
|
|
uint32_t CompactUnwindEncoding = 0;
|
|
|
|
unsigned SubtractInstrIdx = Is64Bit ? 3 : 2;
|
|
unsigned InstrOffset = 0;
|
|
unsigned StackAdjust = 0;
|
|
unsigned StackSize = 0;
|
|
unsigned PrevStackSize = 0;
|
|
unsigned NumDefCFAOffsets = 0;
|
|
|
|
for (unsigned i = 0, e = Instrs.size(); i != e; ++i) {
|
|
const MCCFIInstruction &Inst = Instrs[i];
|
|
|
|
switch (Inst.getOperation()) {
|
|
default:
|
|
// Any other CFI directives indicate a frame that we aren't prepared
|
|
// to represent via compact unwind, so just bail out.
|
|
return 0;
|
|
case MCCFIInstruction::OpDefCfaRegister: {
|
|
// Defines a frame pointer. E.g.
|
|
//
|
|
// movq %rsp, %rbp
|
|
// L0:
|
|
// .cfi_def_cfa_register %rbp
|
|
//
|
|
HasFP = true;
|
|
assert(MRI.getLLVMRegNum(Inst.getRegister(), true) ==
|
|
(Is64Bit ? X86::RBP : X86::EBP) && "Invalid frame pointer!");
|
|
|
|
// Reset the counts.
|
|
memset(SavedRegs, 0, sizeof(SavedRegs));
|
|
StackAdjust = 0;
|
|
SavedRegIdx = 0;
|
|
InstrOffset += MoveInstrSize;
|
|
break;
|
|
}
|
|
case MCCFIInstruction::OpDefCfaOffset: {
|
|
// Defines a new offset for the CFA. E.g.
|
|
//
|
|
// With frame:
|
|
//
|
|
// pushq %rbp
|
|
// L0:
|
|
// .cfi_def_cfa_offset 16
|
|
//
|
|
// Without frame:
|
|
//
|
|
// subq $72, %rsp
|
|
// L0:
|
|
// .cfi_def_cfa_offset 80
|
|
//
|
|
PrevStackSize = StackSize;
|
|
StackSize = std::abs(Inst.getOffset()) / StackDivide;
|
|
++NumDefCFAOffsets;
|
|
break;
|
|
}
|
|
case MCCFIInstruction::OpOffset: {
|
|
// Defines a "push" of a callee-saved register. E.g.
|
|
//
|
|
// pushq %r15
|
|
// pushq %r14
|
|
// pushq %rbx
|
|
// L0:
|
|
// subq $120, %rsp
|
|
// L1:
|
|
// .cfi_offset %rbx, -40
|
|
// .cfi_offset %r14, -32
|
|
// .cfi_offset %r15, -24
|
|
//
|
|
if (SavedRegIdx == CU_NUM_SAVED_REGS)
|
|
// If there are too many saved registers, we cannot use a compact
|
|
// unwind encoding.
|
|
return CU::UNWIND_MODE_DWARF;
|
|
|
|
unsigned Reg = MRI.getLLVMRegNum(Inst.getRegister(), true);
|
|
SavedRegs[SavedRegIdx++] = Reg;
|
|
StackAdjust += OffsetSize;
|
|
InstrOffset += PushInstrSize(Reg);
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
StackAdjust /= StackDivide;
|
|
|
|
if (HasFP) {
|
|
if ((StackAdjust & 0xFF) != StackAdjust)
|
|
// Offset was too big for a compact unwind encoding.
|
|
return CU::UNWIND_MODE_DWARF;
|
|
|
|
// Get the encoding of the saved registers when we have a frame pointer.
|
|
uint32_t RegEnc = encodeCompactUnwindRegistersWithFrame();
|
|
if (RegEnc == ~0U) return CU::UNWIND_MODE_DWARF;
|
|
|
|
CompactUnwindEncoding |= CU::UNWIND_MODE_BP_FRAME;
|
|
CompactUnwindEncoding |= (StackAdjust & 0xFF) << 16;
|
|
CompactUnwindEncoding |= RegEnc & CU::UNWIND_BP_FRAME_REGISTERS;
|
|
} else {
|
|
// If the amount of the stack allocation is the size of a register, then
|
|
// we "push" the RAX/EAX register onto the stack instead of adjusting the
|
|
// stack pointer with a SUB instruction. We don't support the push of the
|
|
// RAX/EAX register with compact unwind. So we check for that situation
|
|
// here.
|
|
if ((NumDefCFAOffsets == SavedRegIdx + 1 &&
|
|
StackSize - PrevStackSize == 1) ||
|
|
(Instrs.size() == 1 && NumDefCFAOffsets == 1 && StackSize == 2))
|
|
return CU::UNWIND_MODE_DWARF;
|
|
|
|
SubtractInstrIdx += InstrOffset;
|
|
++StackAdjust;
|
|
|
|
if ((StackSize & 0xFF) == StackSize) {
|
|
// Frameless stack with a small stack size.
|
|
CompactUnwindEncoding |= CU::UNWIND_MODE_STACK_IMMD;
|
|
|
|
// Encode the stack size.
|
|
CompactUnwindEncoding |= (StackSize & 0xFF) << 16;
|
|
} else {
|
|
if ((StackAdjust & 0x7) != StackAdjust)
|
|
// The extra stack adjustments are too big for us to handle.
|
|
return CU::UNWIND_MODE_DWARF;
|
|
|
|
// Frameless stack with an offset too large for us to encode compactly.
|
|
CompactUnwindEncoding |= CU::UNWIND_MODE_STACK_IND;
|
|
|
|
// Encode the offset to the nnnnnn value in the 'subl $nnnnnn, ESP'
|
|
// instruction.
|
|
CompactUnwindEncoding |= (SubtractInstrIdx & 0xFF) << 16;
|
|
|
|
// Encode any extra stack stack adjustments (done via push
|
|
// instructions).
|
|
CompactUnwindEncoding |= (StackAdjust & 0x7) << 13;
|
|
}
|
|
|
|
// Encode the number of registers saved. (Reverse the list first.)
|
|
std::reverse(&SavedRegs[0], &SavedRegs[SavedRegIdx]);
|
|
CompactUnwindEncoding |= (SavedRegIdx & 0x7) << 10;
|
|
|
|
// Get the encoding of the saved registers when we don't have a frame
|
|
// pointer.
|
|
uint32_t RegEnc = encodeCompactUnwindRegistersWithoutFrame(SavedRegIdx);
|
|
if (RegEnc == ~0U) return CU::UNWIND_MODE_DWARF;
|
|
|
|
// Encode the register encoding.
|
|
CompactUnwindEncoding |=
|
|
RegEnc & CU::UNWIND_FRAMELESS_STACK_REG_PERMUTATION;
|
|
}
|
|
|
|
return CompactUnwindEncoding;
|
|
}
|
|
|
|
private:
|
|
/// \brief Get the compact unwind number for a given register. The number
|
|
/// corresponds to the enum lists in compact_unwind_encoding.h.
|
|
int getCompactUnwindRegNum(unsigned Reg) const {
|
|
static const MCPhysReg CU32BitRegs[7] = {
|
|
X86::EBX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::EBP, 0
|
|
};
|
|
static const MCPhysReg CU64BitRegs[] = {
|
|
X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
|
|
};
|
|
const MCPhysReg *CURegs = Is64Bit ? CU64BitRegs : CU32BitRegs;
|
|
for (int Idx = 1; *CURegs; ++CURegs, ++Idx)
|
|
if (*CURegs == Reg)
|
|
return Idx;
|
|
|
|
return -1;
|
|
}
|
|
|
|
/// \brief Return the registers encoded for a compact encoding with a frame
|
|
/// pointer.
|
|
uint32_t encodeCompactUnwindRegistersWithFrame() const {
|
|
// Encode the registers in the order they were saved --- 3-bits per
|
|
// register. The list of saved registers is assumed to be in reverse
|
|
// order. The registers are numbered from 1 to CU_NUM_SAVED_REGS.
|
|
uint32_t RegEnc = 0;
|
|
for (int i = 0, Idx = 0; i != CU_NUM_SAVED_REGS; ++i) {
|
|
unsigned Reg = SavedRegs[i];
|
|
if (Reg == 0) break;
|
|
|
|
int CURegNum = getCompactUnwindRegNum(Reg);
|
|
if (CURegNum == -1) return ~0U;
|
|
|
|
// Encode the 3-bit register number in order, skipping over 3-bits for
|
|
// each register.
|
|
RegEnc |= (CURegNum & 0x7) << (Idx++ * 3);
|
|
}
|
|
|
|
assert((RegEnc & 0x3FFFF) == RegEnc &&
|
|
"Invalid compact register encoding!");
|
|
return RegEnc;
|
|
}
|
|
|
|
/// \brief Create the permutation encoding used with frameless stacks. It is
|
|
/// passed the number of registers to be saved and an array of the registers
|
|
/// saved.
|
|
uint32_t encodeCompactUnwindRegistersWithoutFrame(unsigned RegCount) const {
|
|
// The saved registers are numbered from 1 to 6. In order to encode the
|
|
// order in which they were saved, we re-number them according to their
|
|
// place in the register order. The re-numbering is relative to the last
|
|
// re-numbered register. E.g., if we have registers {6, 2, 4, 5} saved in
|
|
// that order:
|
|
//
|
|
// Orig Re-Num
|
|
// ---- ------
|
|
// 6 6
|
|
// 2 2
|
|
// 4 3
|
|
// 5 3
|
|
//
|
|
for (unsigned i = 0; i < RegCount; ++i) {
|
|
int CUReg = getCompactUnwindRegNum(SavedRegs[i]);
|
|
if (CUReg == -1) return ~0U;
|
|
SavedRegs[i] = CUReg;
|
|
}
|
|
|
|
// Reverse the list.
|
|
std::reverse(&SavedRegs[0], &SavedRegs[CU_NUM_SAVED_REGS]);
|
|
|
|
uint32_t RenumRegs[CU_NUM_SAVED_REGS];
|
|
for (unsigned i = CU_NUM_SAVED_REGS - RegCount; i < CU_NUM_SAVED_REGS; ++i){
|
|
unsigned Countless = 0;
|
|
for (unsigned j = CU_NUM_SAVED_REGS - RegCount; j < i; ++j)
|
|
if (SavedRegs[j] < SavedRegs[i])
|
|
++Countless;
|
|
|
|
RenumRegs[i] = SavedRegs[i] - Countless - 1;
|
|
}
|
|
|
|
// Take the renumbered values and encode them into a 10-bit number.
|
|
uint32_t permutationEncoding = 0;
|
|
switch (RegCount) {
|
|
case 6:
|
|
permutationEncoding |= 120 * RenumRegs[0] + 24 * RenumRegs[1]
|
|
+ 6 * RenumRegs[2] + 2 * RenumRegs[3]
|
|
+ RenumRegs[4];
|
|
break;
|
|
case 5:
|
|
permutationEncoding |= 120 * RenumRegs[1] + 24 * RenumRegs[2]
|
|
+ 6 * RenumRegs[3] + 2 * RenumRegs[4]
|
|
+ RenumRegs[5];
|
|
break;
|
|
case 4:
|
|
permutationEncoding |= 60 * RenumRegs[2] + 12 * RenumRegs[3]
|
|
+ 3 * RenumRegs[4] + RenumRegs[5];
|
|
break;
|
|
case 3:
|
|
permutationEncoding |= 20 * RenumRegs[3] + 4 * RenumRegs[4]
|
|
+ RenumRegs[5];
|
|
break;
|
|
case 2:
|
|
permutationEncoding |= 5 * RenumRegs[4] + RenumRegs[5];
|
|
break;
|
|
case 1:
|
|
permutationEncoding |= RenumRegs[5];
|
|
break;
|
|
}
|
|
|
|
assert((permutationEncoding & 0x3FF) == permutationEncoding &&
|
|
"Invalid compact register encoding!");
|
|
return permutationEncoding;
|
|
}
|
|
|
|
public:
|
|
DarwinX86AsmBackend(const Target &T, const MCRegisterInfo &MRI, StringRef CPU,
|
|
bool Is64Bit)
|
|
: X86AsmBackend(T, CPU), MRI(MRI), Is64Bit(Is64Bit) {
|
|
memset(SavedRegs, 0, sizeof(SavedRegs));
|
|
OffsetSize = Is64Bit ? 8 : 4;
|
|
MoveInstrSize = Is64Bit ? 3 : 2;
|
|
StackDivide = Is64Bit ? 8 : 4;
|
|
}
|
|
};
|
|
|
|
class DarwinX86_32AsmBackend : public DarwinX86AsmBackend {
|
|
public:
|
|
DarwinX86_32AsmBackend(const Target &T, const MCRegisterInfo &MRI,
|
|
StringRef CPU)
|
|
: DarwinX86AsmBackend(T, MRI, CPU, false) {}
|
|
|
|
MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
|
|
return createX86MachObjectWriter(OS, /*Is64Bit=*/false,
|
|
MachO::CPU_TYPE_I386,
|
|
MachO::CPU_SUBTYPE_I386_ALL);
|
|
}
|
|
|
|
/// \brief Generate the compact unwind encoding for the CFI instructions.
|
|
uint32_t generateCompactUnwindEncoding(
|
|
ArrayRef<MCCFIInstruction> Instrs) const override {
|
|
return generateCompactUnwindEncodingImpl(Instrs);
|
|
}
|
|
};
|
|
|
|
class DarwinX86_64AsmBackend : public DarwinX86AsmBackend {
|
|
const MachO::CPUSubTypeX86 Subtype;
|
|
public:
|
|
DarwinX86_64AsmBackend(const Target &T, const MCRegisterInfo &MRI,
|
|
StringRef CPU, MachO::CPUSubTypeX86 st)
|
|
: DarwinX86AsmBackend(T, MRI, CPU, true), Subtype(st) {}
|
|
|
|
MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
|
|
return createX86MachObjectWriter(OS, /*Is64Bit=*/true,
|
|
MachO::CPU_TYPE_X86_64, Subtype);
|
|
}
|
|
|
|
/// \brief Generate the compact unwind encoding for the CFI instructions.
|
|
uint32_t generateCompactUnwindEncoding(
|
|
ArrayRef<MCCFIInstruction> Instrs) const override {
|
|
return generateCompactUnwindEncodingImpl(Instrs);
|
|
}
|
|
};
|
|
|
|
} // end anonymous namespace
|
|
|
|
MCAsmBackend *llvm::createX86_32AsmBackend(const Target &T,
|
|
const MCRegisterInfo &MRI,
|
|
const Triple &TheTriple,
|
|
StringRef CPU) {
|
|
if (TheTriple.isOSBinFormatMachO())
|
|
return new DarwinX86_32AsmBackend(T, MRI, CPU);
|
|
|
|
if (TheTriple.isOSWindows() && TheTriple.isOSBinFormatCOFF())
|
|
return new WindowsX86AsmBackend(T, false, CPU);
|
|
|
|
uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
|
|
|
|
if (TheTriple.isOSIAMCU())
|
|
return new ELFX86_IAMCUAsmBackend(T, OSABI, CPU);
|
|
|
|
return new ELFX86_32AsmBackend(T, OSABI, CPU);
|
|
}
|
|
|
|
MCAsmBackend *llvm::createX86_64AsmBackend(const Target &T,
|
|
const MCRegisterInfo &MRI,
|
|
const Triple &TheTriple,
|
|
StringRef CPU) {
|
|
if (TheTriple.isOSBinFormatMachO()) {
|
|
MachO::CPUSubTypeX86 CS =
|
|
StringSwitch<MachO::CPUSubTypeX86>(TheTriple.getArchName())
|
|
.Case("x86_64h", MachO::CPU_SUBTYPE_X86_64_H)
|
|
.Default(MachO::CPU_SUBTYPE_X86_64_ALL);
|
|
return new DarwinX86_64AsmBackend(T, MRI, CPU, CS);
|
|
}
|
|
|
|
if (TheTriple.isOSWindows() && TheTriple.isOSBinFormatCOFF())
|
|
return new WindowsX86AsmBackend(T, true, CPU);
|
|
|
|
uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
|
|
|
|
if (TheTriple.getEnvironment() == Triple::GNUX32)
|
|
return new ELFX86_X32AsmBackend(T, OSABI, CPU);
|
|
return new ELFX86_64AsmBackend(T, OSABI, CPU);
|
|
}
|