forked from OSchip/llvm-project
160 lines
6.3 KiB
TableGen
160 lines
6.3 KiB
TableGen
//===- SPUNodes.td - Specialized SelectionDAG nodes used for CellSPU ------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Type profiles and SelectionDAG nodes used by CellSPU
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//
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//===----------------------------------------------------------------------===//
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// Type profile for a call sequence
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def SDT_SPUCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
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// SPU_GenControl: Type profile for generating control words for insertions
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def SPU_GenControl : SDTypeProfile<1, 1, []>;
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def SPUshufmask : SDNode<"SPUISD::SHUFFLE_MASK", SPU_GenControl, []>;
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def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPUCallSeq,
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[SDNPHasChain, SDNPOutGlue]>;
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def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPUCallSeq,
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[SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
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//===----------------------------------------------------------------------===//
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// Operand constraints:
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//===----------------------------------------------------------------------===//
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def SDT_SPUCall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
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def SPUcall : SDNode<"SPUISD::CALL", SDT_SPUCall,
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[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
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SDNPVariadic]>;
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// Operand type constraints for vector shuffle/permute operations
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def SDT_SPUshuffle : SDTypeProfile<1, 3, [
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SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>
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]>;
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// Vector binary operator type constraints (needs a further constraint to
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// ensure that operand 0 is a vector...):
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def SPUVecBinop: SDTypeProfile<1, 2, [
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SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>
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]>;
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// Trinary operators, e.g., addx, carry generate
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def SPUIntTrinaryOp : SDTypeProfile<1, 3, [
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SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisInt<0>
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]>;
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// SELECT_MASK type constraints: There are several variations for the various
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// vector types (this avoids having to bit_convert all over the place.)
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def SPUselmask_type: SDTypeProfile<1, 1, [
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SDTCisInt<1>
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]>;
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// SELB type constraints:
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def SPUselb_type: SDTypeProfile<1, 3, [
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SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisSameAs<0, 3> ]>;
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// SPU Vector shift pseudo-instruction type constraints
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def SPUvecshift_type: SDTypeProfile<1, 2, [
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SDTCisSameAs<0, 1>, SDTCisInt<2>]>;
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// "marker" type for i64 operators that need a shuffle mask
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// (i.e., uses cg or bg or another instruction that needs to
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// use shufb to get things in the right place.)
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// Op0: The result
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// Op1, 2: LHS, RHS
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// Op3: Carry-generate shuffle mask
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def SPUmarker_type : SDTypeProfile<1, 3, [
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SDTCisInt<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2> ]>;
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//===----------------------------------------------------------------------===//
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// Synthetic/pseudo-instructions
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//===----------------------------------------------------------------------===//
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// SPU CNTB:
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def SPUcntb : SDNode<"SPUISD::CNTB", SDTIntUnaryOp>;
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// SPU vector shuffle node, matched by the SPUISD::SHUFB enum (see
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// SPUISelLowering.h):
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def SPUshuffle: SDNode<"SPUISD::SHUFB", SDT_SPUshuffle, []>;
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// Vector shifts (ISD::SHL,SRL,SRA are for _integers_ only):
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def SPUvec_shl: SDNode<"ISD::SHL", SPUvecshift_type, []>;
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def SPUvec_srl: SDNode<"ISD::SRL", SPUvecshift_type, []>;
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def SPUvec_sra: SDNode<"ISD::SRA", SPUvecshift_type, []>;
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def SPUvec_rotl: SDNode<"SPUISD::VEC_ROTL", SPUvecshift_type, []>;
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def SPUvec_rotr: SDNode<"SPUISD::VEC_ROTR", SPUvecshift_type, []>;
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// Vector rotate left, bits shifted out of the left are rotated in on the right
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def SPUrotbytes_left: SDNode<"SPUISD::ROTBYTES_LEFT",
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SPUvecshift_type, []>;
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// Vector rotate left by bytes, but the count is given in bits and the SPU
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// internally converts it to bytes (saves an instruction to mask off lower
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// three bits)
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def SPUrotbytes_left_bits : SDNode<"SPUISD::ROTBYTES_LEFT_BITS",
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SPUvecshift_type>;
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// Shift entire quad left by bytes/bits. Zeros are shifted in on the right
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// SHL_BITS the same as SHL for i128, but ISD::SHL is not implemented for i128
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def SPUshlquad_l_bytes: SDNode<"SPUISD::SHL_BYTES", SPUvecshift_type, []>;
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def SPUshlquad_l_bits: SDNode<"SPUISD::SHL_BITS", SPUvecshift_type, []>;
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def SPUsrl_bytes: SDNode<"SPUISD::SRL_BYTES", SPUvecshift_type, []>;
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// SPU form select mask for bytes, immediate
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def SPUselmask: SDNode<"SPUISD::SELECT_MASK", SPUselmask_type, []>;
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// SPU select bits instruction
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def SPUselb: SDNode<"SPUISD::SELB", SPUselb_type, []>;
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def SDTprefslot2vec: SDTypeProfile<1, 1, []>;
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def SPUprefslot2vec: SDNode<"SPUISD::PREFSLOT2VEC", SDTprefslot2vec, []>;
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def SPU_vec_demote : SDTypeProfile<1, 1, []>;
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def SPUvec2prefslot: SDNode<"SPUISD::VEC2PREFSLOT", SPU_vec_demote, []>;
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// Address high and low components, used for [r+r] type addressing
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def SPUhi : SDNode<"SPUISD::Hi", SDTIntBinOp, []>;
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def SPUlo : SDNode<"SPUISD::Lo", SDTIntBinOp, []>;
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// PC-relative address
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def SPUpcrel : SDNode<"SPUISD::PCRelAddr", SDTIntBinOp, []>;
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// A-Form local store addresses
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def SPUaform : SDNode<"SPUISD::AFormAddr", SDTIntBinOp, []>;
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// Indirect [D-Form "imm($reg)" and X-Form "$reg($reg)"] addresses
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def SPUindirect : SDNode<"SPUISD::IndirectAddr", SDTIntBinOp, []>;
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// i64 markers: supplies extra operands used to generate the i64 operator
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// instruction sequences
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def SPUadd64 : SDNode<"SPUISD::ADD64_MARKER", SPUmarker_type, []>;
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def SPUsub64 : SDNode<"SPUISD::SUB64_MARKER", SPUmarker_type, []>;
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def SPUmul64 : SDNode<"SPUISD::MUL64_MARKER", SPUmarker_type, []>;
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//===----------------------------------------------------------------------===//
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// Constraints: (taken from PPCInstrInfo.td)
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//===----------------------------------------------------------------------===//
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class RegConstraint<string C> {
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string Constraints = C;
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}
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class NoEncode<string E> {
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string DisableEncoding = E;
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}
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//===----------------------------------------------------------------------===//
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// Return (flag isn't quite what it means: the operations are flagged so that
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// instruction scheduling doesn't disassociate them.)
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//===----------------------------------------------------------------------===//
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def retflag : SDNode<"SPUISD::RET_FLAG", SDTNone,
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[SDNPHasChain, SDNPOptInGlue]>;
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