llvm-project/llvm/test/MC/Disassembler/ARM/unpredictable-RSC-arm.txt

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# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | FileCheck %s
# Opcode=261 Name=RSCrs Format=ARM_FORMAT_DPSOREGFRM(5)
# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
# -------------------------------------------------------------------------------------------------
# | 0: 0: 1: 1| 0: 0: 0: 0| 1: 1: 1: 0| 0: 1: 0: 0| 1: 1: 1: 1| 1: 0: 0: 0| 0: 1: 0: 1| 1: 1: 1: 1|
# -------------------------------------------------------------------------------------------------
# if d == 15 || n == 15 || m == 15 || s == 15 then UNPREDICTABLE;
# CHECK: warning: potentially undefined instruction encoding
0x5f 0xf8 0xe4 0x30