llvm-project/llvm/test/MC/Disassembler
Simon Dardis 169df4e24b [mips] Add movep for microMIPS32R6 and fix microMIPS32r3 version
Previously, the 'movep' instruction was defined for microMIPS32r3 and
shared that definition with microMIPS32R6. 'movep' was re-encoded for
microMIPS32r6, so this patch provides the correct encoding.

Secondly, correct the encoding of the 'rs' and 'rt' operands which have
an instruction specific encoding for the registers those operands accept.

Finally, correct the decoding of the 'dst_regs' operand which was extracting
the relevant field from the instruction, but was actually extracting the
field from the alreadly extracted field.

Reviewers: atanasyan

Differential Revision: https://reviews.llvm.org/D39495

llvm-svn: 317475
2017-11-06 12:59:53 +00:00
..
AArch64 [AArch64] v8.3-a complex number support 2017-08-31 09:27:04 +00:00
AMDGPU [AMDGPU][MC][GFX9] Added op_sel support for v_mad_*16, v_fma_f16, v_div_fixup_f16 2017-08-16 15:16:32 +00:00
ARC [ARC] Add ARC backend. 2017-08-24 15:40:33 +00:00
ARM [ARM] Fix disassembly for conditional VMRS and VMSR instructions in ARM mode 2017-10-18 14:47:37 +00:00
Hexagon [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
Lanai [lanai] Add Lanai backend. 2016-03-28 13:09:54 +00:00
Mips [mips] Add movep for microMIPS32R6 and fix microMIPS32r3 version 2017-11-06 12:59:53 +00:00
PowerPC [Power9] Add missing Power9 instructions. 2017-09-19 15:22:36 +00:00
Sparc This change adds co-processor condition branching and conditional traps to the Sparc back-end. 2016-03-09 18:20:21 +00:00
SystemZ [SystemZ] Add support for IBM z14 processor (3/3) 2017-07-17 17:44:20 +00:00
X86 Fix for Bug 34475 - LOCK/REP/REPNE prefixes emitted as instruction on their own. 2017-11-03 15:25:13 +00:00
XCore