forked from OSchip/llvm-project
852 lines
30 KiB
C++
852 lines
30 KiB
C++
//===- HexagonMCInstrInfo.cpp - Hexagon sub-class of MCInst ---------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This class extends MCInstrInfo to allow Hexagon specific MCInstr queries
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//
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//===----------------------------------------------------------------------===//
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#include "HexagonMCInstrInfo.h"
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#include "Hexagon.h"
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#include "HexagonBaseInfo.h"
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#include "HexagonMCChecker.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCInstrItineraries.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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namespace llvm {
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Hexagon::PacketIterator::PacketIterator(MCInstrInfo const &MCII,
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MCInst const &Inst)
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: MCII(MCII), BundleCurrent(Inst.begin() +
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HexagonMCInstrInfo::bundleInstructionsOffset),
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BundleEnd(Inst.end()), DuplexCurrent(Inst.end()), DuplexEnd(Inst.end()) {}
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Hexagon::PacketIterator::PacketIterator(MCInstrInfo const &MCII,
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MCInst const &Inst, std::nullptr_t)
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: MCII(MCII), BundleCurrent(Inst.end()), BundleEnd(Inst.end()),
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DuplexCurrent(Inst.end()), DuplexEnd(Inst.end()) {}
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Hexagon::PacketIterator &Hexagon::PacketIterator::operator++() {
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if (DuplexCurrent != DuplexEnd) {
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++DuplexCurrent;
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if (DuplexCurrent == DuplexEnd) {
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DuplexCurrent = BundleEnd;
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DuplexEnd = BundleEnd;
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}
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return *this;
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}
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++BundleCurrent;
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if (BundleCurrent != BundleEnd) {
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MCInst const &Inst = *BundleCurrent->getInst();
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if (HexagonMCInstrInfo::isDuplex(MCII, Inst)) {
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DuplexCurrent = Inst.begin();
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DuplexEnd = Inst.end();
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}
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}
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return *this;
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}
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MCInst const &Hexagon::PacketIterator::operator*() const {
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if (DuplexCurrent != DuplexEnd)
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return *DuplexCurrent->getInst();
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return *BundleCurrent->getInst();
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}
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bool Hexagon::PacketIterator::operator==(PacketIterator const &Other) const {
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return BundleCurrent == Other.BundleCurrent && BundleEnd == Other.BundleEnd &&
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DuplexCurrent == Other.DuplexCurrent && DuplexEnd == Other.DuplexEnd;
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}
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void HexagonMCInstrInfo::addConstant(MCInst &MI, uint64_t Value,
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MCContext &Context) {
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MI.addOperand(MCOperand::createExpr(MCConstantExpr::create(Value, Context)));
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}
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void HexagonMCInstrInfo::addConstExtender(MCContext &Context,
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MCInstrInfo const &MCII, MCInst &MCB,
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MCInst const &MCI) {
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assert(HexagonMCInstrInfo::isBundle(MCB));
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MCOperand const &exOp =
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MCI.getOperand(HexagonMCInstrInfo::getExtendableOp(MCII, MCI));
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// Create the extender.
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MCInst *XMCI =
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new (Context) MCInst(HexagonMCInstrInfo::deriveExtender(MCII, MCI, exOp));
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MCB.addOperand(MCOperand::createInst(XMCI));
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}
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iterator_range<Hexagon::PacketIterator>
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HexagonMCInstrInfo::bundleInstructions(MCInstrInfo const &MCII,
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MCInst const &MCI) {
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assert(isBundle(MCI));
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return make_range(Hexagon::PacketIterator(MCII, MCI),
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Hexagon::PacketIterator(MCII, MCI, nullptr));
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}
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iterator_range<MCInst::const_iterator>
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HexagonMCInstrInfo::bundleInstructions(MCInst const &MCI) {
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assert(isBundle(MCI));
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return make_range(MCI.begin() + bundleInstructionsOffset, MCI.end());
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}
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size_t HexagonMCInstrInfo::bundleSize(MCInst const &MCI) {
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if (HexagonMCInstrInfo::isBundle(MCI))
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return (MCI.size() - bundleInstructionsOffset);
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else
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return (1);
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}
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bool HexagonMCInstrInfo::canonicalizePacket(MCInstrInfo const &MCII,
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MCSubtargetInfo const &STI,
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MCContext &Context, MCInst &MCB,
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HexagonMCChecker *Check) {
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// Check the bundle for errors.
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bool CheckOk = Check ? Check->check(false) : true;
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if (!CheckOk)
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return false;
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// Examine the packet and convert pairs of instructions to compound
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// instructions when possible.
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if (!HexagonDisableCompound)
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HexagonMCInstrInfo::tryCompound(MCII, STI, Context, MCB);
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HexagonMCShuffle(Context, false, MCII, STI, MCB);
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// Examine the packet and convert pairs of instructions to duplex
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// instructions when possible.
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MCInst InstBundlePreDuplex = MCInst(MCB);
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if (!HexagonDisableDuplex) {
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SmallVector<DuplexCandidate, 8> possibleDuplexes;
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possibleDuplexes =
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HexagonMCInstrInfo::getDuplexPossibilties(MCII, STI, MCB);
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HexagonMCShuffle(Context, MCII, STI, MCB, possibleDuplexes);
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}
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// Examines packet and pad the packet, if needed, when an
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// end-loop is in the bundle.
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HexagonMCInstrInfo::padEndloop(MCB, Context);
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// If compounding and duplexing didn't reduce the size below
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// 4 or less we have a packet that is too big.
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if (HexagonMCInstrInfo::bundleSize(MCB) > HEXAGON_PACKET_SIZE)
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return false;
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// Check the bundle for errors.
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CheckOk = Check ? Check->check(true) : true;
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if (!CheckOk)
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return false;
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HexagonMCShuffle(Context, true, MCII, STI, MCB);
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return true;
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}
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void HexagonMCInstrInfo::clampExtended(MCInstrInfo const &MCII,
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MCContext &Context, MCInst &MCI) {
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assert(HexagonMCInstrInfo::isExtendable(MCII, MCI) ||
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HexagonMCInstrInfo::isExtended(MCII, MCI));
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MCOperand &exOp =
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MCI.getOperand(HexagonMCInstrInfo::getExtendableOp(MCII, MCI));
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// If the extended value is a constant, then use it for the extended and
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// for the extender instructions, masking off the lower 6 bits and
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// including the assumed bits.
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int64_t Value;
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if (exOp.getExpr()->evaluateAsAbsolute(Value)) {
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unsigned Shift = HexagonMCInstrInfo::getExtentAlignment(MCII, MCI);
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exOp.setExpr(HexagonMCExpr::create(
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MCConstantExpr::create((Value & 0x3f) << Shift, Context), Context));
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}
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}
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MCInst HexagonMCInstrInfo::createBundle() {
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MCInst Result;
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Result.setOpcode(Hexagon::BUNDLE);
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Result.addOperand(MCOperand::createImm(0));
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return Result;
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}
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MCInst HexagonMCInstrInfo::deriveExtender(MCInstrInfo const &MCII,
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MCInst const &Inst,
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MCOperand const &MO) {
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assert(HexagonMCInstrInfo::isExtendable(MCII, Inst) ||
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HexagonMCInstrInfo::isExtended(MCII, Inst));
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MCInst XMI;
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XMI.setOpcode(Hexagon::A4_ext);
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if (MO.isImm())
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XMI.addOperand(MCOperand::createImm(MO.getImm() & (~0x3f)));
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else if (MO.isExpr())
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XMI.addOperand(MCOperand::createExpr(MO.getExpr()));
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else
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llvm_unreachable("invalid extendable operand");
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return XMI;
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}
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MCInst *HexagonMCInstrInfo::deriveDuplex(MCContext &Context, unsigned iClass,
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MCInst const &inst0,
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MCInst const &inst1) {
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assert((iClass <= 0xf) && "iClass must have range of 0 to 0xf");
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MCInst *duplexInst = new (Context) MCInst;
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duplexInst->setOpcode(Hexagon::DuplexIClass0 + iClass);
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MCInst *SubInst0 = new (Context) MCInst(deriveSubInst(inst0));
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MCInst *SubInst1 = new (Context) MCInst(deriveSubInst(inst1));
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duplexInst->addOperand(MCOperand::createInst(SubInst0));
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duplexInst->addOperand(MCOperand::createInst(SubInst1));
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return duplexInst;
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}
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MCInst const *HexagonMCInstrInfo::extenderForIndex(MCInst const &MCB,
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size_t Index) {
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assert(Index <= bundleSize(MCB));
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if (Index == 0)
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return nullptr;
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MCInst const *Inst =
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MCB.getOperand(Index + bundleInstructionsOffset - 1).getInst();
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if (isImmext(*Inst))
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return Inst;
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return nullptr;
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}
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void HexagonMCInstrInfo::extendIfNeeded(MCContext &Context,
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MCInstrInfo const &MCII, MCInst &MCB,
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MCInst const &MCI) {
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if (isConstExtended(MCII, MCI))
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addConstExtender(Context, MCII, MCB, MCI);
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}
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HexagonII::MemAccessSize
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HexagonMCInstrInfo::getAccessSize(MCInstrInfo const &MCII, MCInst const &MCI) {
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const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
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return (HexagonII::MemAccessSize((F >> HexagonII::MemAccessSizePos) &
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HexagonII::MemAccesSizeMask));
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}
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MCInstrDesc const &HexagonMCInstrInfo::getDesc(MCInstrInfo const &MCII,
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MCInst const &MCI) {
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return MCII.get(MCI.getOpcode());
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}
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unsigned HexagonMCInstrInfo::getDuplexRegisterNumbering(unsigned Reg) {
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using namespace Hexagon;
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switch (Reg) {
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default:
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llvm_unreachable("unknown duplex register");
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// Rs Rss
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case R0:
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case D0:
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return 0;
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case R1:
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case D1:
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return 1;
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case R2:
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case D2:
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return 2;
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case R3:
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case D3:
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return 3;
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case R4:
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case D8:
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return 4;
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case R5:
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case D9:
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return 5;
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case R6:
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case D10:
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return 6;
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case R7:
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case D11:
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return 7;
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case R16:
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return 8;
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case R17:
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return 9;
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case R18:
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return 10;
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case R19:
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return 11;
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case R20:
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return 12;
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case R21:
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return 13;
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case R22:
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return 14;
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case R23:
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return 15;
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}
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}
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MCExpr const &HexagonMCInstrInfo::getExpr(MCExpr const &Expr) {
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const auto &HExpr = cast<HexagonMCExpr>(Expr);
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assert(HExpr.getExpr());
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return *HExpr.getExpr();
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}
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unsigned short HexagonMCInstrInfo::getExtendableOp(MCInstrInfo const &MCII,
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MCInst const &MCI) {
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const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
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return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask);
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}
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MCOperand const &
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HexagonMCInstrInfo::getExtendableOperand(MCInstrInfo const &MCII,
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MCInst const &MCI) {
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unsigned O = HexagonMCInstrInfo::getExtendableOp(MCII, MCI);
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MCOperand const &MO = MCI.getOperand(O);
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assert((HexagonMCInstrInfo::isExtendable(MCII, MCI) ||
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HexagonMCInstrInfo::isExtended(MCII, MCI)) &&
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(MO.isImm() || MO.isExpr()));
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return (MO);
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}
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unsigned HexagonMCInstrInfo::getExtentAlignment(MCInstrInfo const &MCII,
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MCInst const &MCI) {
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const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
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return ((F >> HexagonII::ExtentAlignPos) & HexagonII::ExtentAlignMask);
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}
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unsigned HexagonMCInstrInfo::getExtentBits(MCInstrInfo const &MCII,
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MCInst const &MCI) {
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const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
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return ((F >> HexagonII::ExtentBitsPos) & HexagonII::ExtentBitsMask);
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}
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/// Return the maximum value of an extendable operand.
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int HexagonMCInstrInfo::getMaxValue(MCInstrInfo const &MCII,
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MCInst const &MCI) {
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const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
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bool S = (F >> HexagonII::ExtentSignedPos) & HexagonII::ExtentSignedMask;
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assert(HexagonMCInstrInfo::isExtendable(MCII, MCI) ||
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HexagonMCInstrInfo::isExtended(MCII, MCI));
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if (S) // if value is signed
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return (1 << (HexagonMCInstrInfo::getExtentBits(MCII, MCI) - 1)) - 1;
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return (1 << HexagonMCInstrInfo::getExtentBits(MCII, MCI)) - 1;
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}
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/// Return the minimum value of an extendable operand.
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int HexagonMCInstrInfo::getMinValue(MCInstrInfo const &MCII,
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MCInst const &MCI) {
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const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
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bool S = (F >> HexagonII::ExtentSignedPos) & HexagonII::ExtentSignedMask;
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assert(HexagonMCInstrInfo::isExtendable(MCII, MCI) ||
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HexagonMCInstrInfo::isExtended(MCII, MCI));
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if (S) // if value is signed
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return -(1 << (HexagonMCInstrInfo::getExtentBits(MCII, MCI) - 1));
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return 0;
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}
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StringRef HexagonMCInstrInfo::getName(MCInstrInfo const &MCII,
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MCInst const &MCI) {
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return MCII.getName(MCI.getOpcode());
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}
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unsigned short HexagonMCInstrInfo::getNewValueOp(MCInstrInfo const &MCII,
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MCInst const &MCI) {
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const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
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return ((F >> HexagonII::NewValueOpPos) & HexagonII::NewValueOpMask);
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}
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MCOperand const &HexagonMCInstrInfo::getNewValueOperand(MCInstrInfo const &MCII,
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MCInst const &MCI) {
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unsigned O = HexagonMCInstrInfo::getNewValueOp(MCII, MCI);
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MCOperand const &MCO = MCI.getOperand(O);
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assert((HexagonMCInstrInfo::isNewValue(MCII, MCI) ||
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HexagonMCInstrInfo::hasNewValue(MCII, MCI)) &&
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MCO.isReg());
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return (MCO);
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}
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/// Return the new value or the newly produced value.
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unsigned short HexagonMCInstrInfo::getNewValueOp2(MCInstrInfo const &MCII,
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MCInst const &MCI) {
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const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
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return ((F >> HexagonII::NewValueOpPos2) & HexagonII::NewValueOpMask2);
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}
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MCOperand const &
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HexagonMCInstrInfo::getNewValueOperand2(MCInstrInfo const &MCII,
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MCInst const &MCI) {
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unsigned O = HexagonMCInstrInfo::getNewValueOp2(MCII, MCI);
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MCOperand const &MCO = MCI.getOperand(O);
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assert((HexagonMCInstrInfo::isNewValue(MCII, MCI) ||
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HexagonMCInstrInfo::hasNewValue2(MCII, MCI)) &&
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MCO.isReg());
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return (MCO);
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}
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/// Return the Hexagon ISA class for the insn.
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unsigned HexagonMCInstrInfo::getType(MCInstrInfo const &MCII,
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MCInst const &MCI) {
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const uint64_t F = MCII.get(MCI.getOpcode()).TSFlags;
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return ((F >> HexagonII::TypePos) & HexagonII::TypeMask);
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}
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/// Return the slots this instruction can execute out of
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unsigned HexagonMCInstrInfo::getUnits(MCInstrInfo const &MCII,
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MCSubtargetInfo const &STI,
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MCInst const &MCI) {
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const InstrItinerary *II = STI.getSchedModel().InstrItineraries;
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int SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass();
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return ((II[SchedClass].FirstStage + HexagonStages)->getUnits());
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}
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/// Return the slots this instruction consumes in addition to
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/// the slot(s) it can execute out of
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unsigned HexagonMCInstrInfo::getOtherReservedSlots(MCInstrInfo const &MCII,
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MCSubtargetInfo const &STI,
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MCInst const &MCI) {
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const InstrItinerary *II = STI.getSchedModel().InstrItineraries;
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int SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass();
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unsigned Slots = 0;
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// FirstStage are slots that this instruction can execute in.
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// FirstStage+1 are slots that are also consumed by this instruction.
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// For example: vmemu can only execute in slot 0 but also consumes slot 1.
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for (unsigned Stage = II[SchedClass].FirstStage + 1;
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Stage < II[SchedClass].LastStage; ++Stage) {
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unsigned Units = (Stage + HexagonStages)->getUnits();
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if (Units > HexagonGetLastSlot())
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break;
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// fyi: getUnits() will return 0x1, 0x2, 0x4 or 0x8
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Slots |= Units;
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}
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// if 0 is returned, then no additional slots are consumed by this inst.
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return Slots;
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}
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bool HexagonMCInstrInfo::hasDuplex(MCInstrInfo const &MCII, MCInst const &MCI) {
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if (!HexagonMCInstrInfo::isBundle(MCI))
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return false;
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for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCII, MCI)) {
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if (HexagonMCInstrInfo::isDuplex(MCII, I))
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return true;
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}
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return false;
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}
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bool HexagonMCInstrInfo::hasExtenderForIndex(MCInst const &MCB, size_t Index) {
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return extenderForIndex(MCB, Index) != nullptr;
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}
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bool HexagonMCInstrInfo::hasImmExt( MCInst const &MCI) {
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if (!HexagonMCInstrInfo::isBundle(MCI))
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return false;
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for (const auto &I : HexagonMCInstrInfo::bundleInstructions(MCI)) {
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if (isImmext(*I.getInst()))
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return true;
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}
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return false;
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}
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/// Return whether the insn produces a value.
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bool HexagonMCInstrInfo::hasNewValue(MCInstrInfo const &MCII,
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MCInst const &MCI) {
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const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
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return ((F >> HexagonII::hasNewValuePos) & HexagonII::hasNewValueMask);
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}
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/// Return whether the insn produces a second value.
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bool HexagonMCInstrInfo::hasNewValue2(MCInstrInfo const &MCII,
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MCInst const &MCI) {
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const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
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return ((F >> HexagonII::hasNewValuePos2) & HexagonII::hasNewValueMask2);
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}
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MCInst const &HexagonMCInstrInfo::instruction(MCInst const &MCB, size_t Index) {
|
|
assert(isBundle(MCB));
|
|
assert(Index < HEXAGON_PACKET_SIZE);
|
|
return *MCB.getOperand(bundleInstructionsOffset + Index).getInst();
|
|
}
|
|
|
|
/// Return where the instruction is an accumulator.
|
|
bool HexagonMCInstrInfo::isAccumulator(MCInstrInfo const &MCII,
|
|
MCInst const &MCI) {
|
|
const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
|
|
return ((F >> HexagonII::AccumulatorPos) & HexagonII::AccumulatorMask);
|
|
}
|
|
|
|
bool HexagonMCInstrInfo::isBundle(MCInst const &MCI) {
|
|
auto Result = Hexagon::BUNDLE == MCI.getOpcode();
|
|
assert(!Result || (MCI.size() > 0 && MCI.getOperand(0).isImm()));
|
|
return Result;
|
|
}
|
|
|
|
bool HexagonMCInstrInfo::isConstExtended(MCInstrInfo const &MCII,
|
|
MCInst const &MCI) {
|
|
if (HexagonMCInstrInfo::isExtended(MCII, MCI))
|
|
return true;
|
|
if (!HexagonMCInstrInfo::isExtendable(MCII, MCI))
|
|
return false;
|
|
MCOperand const &MO = HexagonMCInstrInfo::getExtendableOperand(MCII, MCI);
|
|
if (isa<HexagonMCExpr>(MO.getExpr()) &&
|
|
HexagonMCInstrInfo::mustExtend(*MO.getExpr()))
|
|
return true;
|
|
// Branch insns are handled as necessary by relaxation.
|
|
if ((HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeJ) ||
|
|
(HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeCJ &&
|
|
HexagonMCInstrInfo::getDesc(MCII, MCI).isBranch()) ||
|
|
(HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeNCJ &&
|
|
HexagonMCInstrInfo::getDesc(MCII, MCI).isBranch()))
|
|
return false;
|
|
// Otherwise loop instructions and other CR insts are handled by relaxation
|
|
else if ((HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeCR) &&
|
|
(MCI.getOpcode() != Hexagon::C4_addipc))
|
|
return false;
|
|
|
|
assert(!MO.isImm());
|
|
if (isa<HexagonMCExpr>(MO.getExpr()) &&
|
|
HexagonMCInstrInfo::mustNotExtend(*MO.getExpr()))
|
|
return false;
|
|
int64_t Value;
|
|
if (!MO.getExpr()->evaluateAsAbsolute(Value))
|
|
return true;
|
|
int MinValue = HexagonMCInstrInfo::getMinValue(MCII, MCI);
|
|
int MaxValue = HexagonMCInstrInfo::getMaxValue(MCII, MCI);
|
|
return (MinValue > Value || Value > MaxValue);
|
|
}
|
|
|
|
bool HexagonMCInstrInfo::isCanon(MCInstrInfo const &MCII, MCInst const &MCI) {
|
|
return !HexagonMCInstrInfo::getDesc(MCII, MCI).isPseudo() &&
|
|
!HexagonMCInstrInfo::isPrefix(MCII, MCI);
|
|
}
|
|
|
|
bool HexagonMCInstrInfo::isCofMax1(MCInstrInfo const &MCII, MCInst const &MCI) {
|
|
const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
|
|
return ((F >> HexagonII::CofMax1Pos) & HexagonII::CofMax1Mask);
|
|
}
|
|
|
|
bool HexagonMCInstrInfo::isCompound(MCInstrInfo const &MCII,
|
|
MCInst const &MCI) {
|
|
return (getType(MCII, MCI) == HexagonII::TypeCJ);
|
|
}
|
|
|
|
bool HexagonMCInstrInfo::isCVINew(MCInstrInfo const &MCII, MCInst const &MCI) {
|
|
const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
|
|
return ((F >> HexagonII::CVINewPos) & HexagonII::CVINewMask);
|
|
}
|
|
|
|
bool HexagonMCInstrInfo::isDblRegForSubInst(unsigned Reg) {
|
|
return ((Reg >= Hexagon::D0 && Reg <= Hexagon::D3) ||
|
|
(Reg >= Hexagon::D8 && Reg <= Hexagon::D11));
|
|
}
|
|
|
|
bool HexagonMCInstrInfo::isDuplex(MCInstrInfo const &MCII, MCInst const &MCI) {
|
|
return HexagonII::TypeDUPLEX == HexagonMCInstrInfo::getType(MCII, MCI);
|
|
}
|
|
|
|
bool HexagonMCInstrInfo::isExtendable(MCInstrInfo const &MCII,
|
|
MCInst const &MCI) {
|
|
uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
|
|
return (F >> HexagonII::ExtendablePos) & HexagonII::ExtendableMask;
|
|
}
|
|
|
|
bool HexagonMCInstrInfo::isExtended(MCInstrInfo const &MCII,
|
|
MCInst const &MCI) {
|
|
uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
|
|
return (F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask;
|
|
}
|
|
|
|
bool HexagonMCInstrInfo::isFloat(MCInstrInfo const &MCII, MCInst const &MCI) {
|
|
const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
|
|
return ((F >> HexagonII::FPPos) & HexagonII::FPMask);
|
|
}
|
|
|
|
bool HexagonMCInstrInfo::isImmext(MCInst const &MCI) {
|
|
return MCI.getOpcode() == Hexagon::A4_ext;
|
|
}
|
|
|
|
bool HexagonMCInstrInfo::isInnerLoop(MCInst const &MCI) {
|
|
assert(isBundle(MCI));
|
|
int64_t Flags = MCI.getOperand(0).getImm();
|
|
return (Flags & innerLoopMask) != 0;
|
|
}
|
|
|
|
bool HexagonMCInstrInfo::isIntReg(unsigned Reg) {
|
|
return (Reg >= Hexagon::R0 && Reg <= Hexagon::R31);
|
|
}
|
|
|
|
bool HexagonMCInstrInfo::isIntRegForSubInst(unsigned Reg) {
|
|
return ((Reg >= Hexagon::R0 && Reg <= Hexagon::R7) ||
|
|
(Reg >= Hexagon::R16 && Reg <= Hexagon::R23));
|
|
}
|
|
|
|
/// Return whether the insn expects newly produced value.
|
|
bool HexagonMCInstrInfo::isNewValue(MCInstrInfo const &MCII,
|
|
MCInst const &MCI) {
|
|
const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
|
|
return ((F >> HexagonII::NewValuePos) & HexagonII::NewValueMask);
|
|
}
|
|
|
|
/// Return whether the operand is extendable.
|
|
bool HexagonMCInstrInfo::isOpExtendable(MCInstrInfo const &MCII,
|
|
MCInst const &MCI, unsigned short O) {
|
|
return (O == HexagonMCInstrInfo::getExtendableOp(MCII, MCI));
|
|
}
|
|
|
|
bool HexagonMCInstrInfo::isOuterLoop(MCInst const &MCI) {
|
|
assert(isBundle(MCI));
|
|
int64_t Flags = MCI.getOperand(0).getImm();
|
|
return (Flags & outerLoopMask) != 0;
|
|
}
|
|
|
|
bool HexagonMCInstrInfo::isPredicated(MCInstrInfo const &MCII,
|
|
MCInst const &MCI) {
|
|
const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
|
|
return ((F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
|
|
}
|
|
|
|
bool HexagonMCInstrInfo::isPrefix(MCInstrInfo const &MCII, MCInst const &MCI) {
|
|
return HexagonII::TypeEXTENDER == HexagonMCInstrInfo::getType(MCII, MCI);
|
|
}
|
|
|
|
bool HexagonMCInstrInfo::isPredicateLate(MCInstrInfo const &MCII,
|
|
MCInst const &MCI) {
|
|
const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
|
|
return (F >> HexagonII::PredicateLatePos & HexagonII::PredicateLateMask);
|
|
}
|
|
|
|
/// Return whether the insn is newly predicated.
|
|
bool HexagonMCInstrInfo::isPredicatedNew(MCInstrInfo const &MCII,
|
|
MCInst const &MCI) {
|
|
const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
|
|
return ((F >> HexagonII::PredicatedNewPos) & HexagonII::PredicatedNewMask);
|
|
}
|
|
|
|
bool HexagonMCInstrInfo::isPredicatedTrue(MCInstrInfo const &MCII,
|
|
MCInst const &MCI) {
|
|
const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
|
|
return (
|
|
!((F >> HexagonII::PredicatedFalsePos) & HexagonII::PredicatedFalseMask));
|
|
}
|
|
|
|
bool HexagonMCInstrInfo::isPredReg(unsigned Reg) {
|
|
return (Reg >= Hexagon::P0 && Reg <= Hexagon::P3_0);
|
|
}
|
|
|
|
/// Return whether the insn can be packaged only with A and X-type insns.
|
|
bool HexagonMCInstrInfo::isSoloAX(MCInstrInfo const &MCII, MCInst const &MCI) {
|
|
const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
|
|
return ((F >> HexagonII::SoloAXPos) & HexagonII::SoloAXMask);
|
|
}
|
|
|
|
/// Return whether the insn can be packaged only with an A-type insn in slot #1.
|
|
bool HexagonMCInstrInfo::isSoloAin1(MCInstrInfo const &MCII,
|
|
MCInst const &MCI) {
|
|
const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
|
|
return ((F >> HexagonII::SoloAin1Pos) & HexagonII::SoloAin1Mask);
|
|
}
|
|
|
|
/// Return whether the insn is solo, i.e., cannot be in a packet.
|
|
bool HexagonMCInstrInfo::isSolo(MCInstrInfo const &MCII, MCInst const &MCI) {
|
|
const uint64_t F = MCII.get(MCI.getOpcode()).TSFlags;
|
|
return ((F >> HexagonII::SoloPos) & HexagonII::SoloMask);
|
|
}
|
|
|
|
bool HexagonMCInstrInfo::isMemReorderDisabled(MCInst const &MCI) {
|
|
assert(isBundle(MCI));
|
|
auto Flags = MCI.getOperand(0).getImm();
|
|
return (Flags & memReorderDisabledMask) != 0;
|
|
}
|
|
|
|
bool HexagonMCInstrInfo::isMemStoreReorderEnabled(MCInst const &MCI) {
|
|
assert(isBundle(MCI));
|
|
auto Flags = MCI.getOperand(0).getImm();
|
|
return (Flags & memStoreReorderEnabledMask) != 0;
|
|
}
|
|
|
|
bool HexagonMCInstrInfo::isSubInstruction(MCInst const &MCI) {
|
|
switch (MCI.getOpcode()) {
|
|
default:
|
|
return false;
|
|
case Hexagon::SA1_addi:
|
|
case Hexagon::SA1_addrx:
|
|
case Hexagon::SA1_addsp:
|
|
case Hexagon::SA1_and1:
|
|
case Hexagon::SA1_clrf:
|
|
case Hexagon::SA1_clrfnew:
|
|
case Hexagon::SA1_clrt:
|
|
case Hexagon::SA1_clrtnew:
|
|
case Hexagon::SA1_cmpeqi:
|
|
case Hexagon::SA1_combine0i:
|
|
case Hexagon::SA1_combine1i:
|
|
case Hexagon::SA1_combine2i:
|
|
case Hexagon::SA1_combine3i:
|
|
case Hexagon::SA1_combinerz:
|
|
case Hexagon::SA1_combinezr:
|
|
case Hexagon::SA1_dec:
|
|
case Hexagon::SA1_inc:
|
|
case Hexagon::SA1_seti:
|
|
case Hexagon::SA1_setin1:
|
|
case Hexagon::SA1_sxtb:
|
|
case Hexagon::SA1_sxth:
|
|
case Hexagon::SA1_tfr:
|
|
case Hexagon::SA1_zxtb:
|
|
case Hexagon::SA1_zxth:
|
|
case Hexagon::SL1_loadri_io:
|
|
case Hexagon::SL1_loadrub_io:
|
|
case Hexagon::SL2_deallocframe:
|
|
case Hexagon::SL2_jumpr31:
|
|
case Hexagon::SL2_jumpr31_f:
|
|
case Hexagon::SL2_jumpr31_fnew:
|
|
case Hexagon::SL2_jumpr31_t:
|
|
case Hexagon::SL2_jumpr31_tnew:
|
|
case Hexagon::SL2_loadrb_io:
|
|
case Hexagon::SL2_loadrd_sp:
|
|
case Hexagon::SL2_loadrh_io:
|
|
case Hexagon::SL2_loadri_sp:
|
|
case Hexagon::SL2_loadruh_io:
|
|
case Hexagon::SL2_return:
|
|
case Hexagon::SL2_return_f:
|
|
case Hexagon::SL2_return_fnew:
|
|
case Hexagon::SL2_return_t:
|
|
case Hexagon::SL2_return_tnew:
|
|
case Hexagon::SS1_storeb_io:
|
|
case Hexagon::SS1_storew_io:
|
|
case Hexagon::SS2_allocframe:
|
|
case Hexagon::SS2_storebi0:
|
|
case Hexagon::SS2_storebi1:
|
|
case Hexagon::SS2_stored_sp:
|
|
case Hexagon::SS2_storeh_io:
|
|
case Hexagon::SS2_storew_sp:
|
|
case Hexagon::SS2_storewi0:
|
|
case Hexagon::SS2_storewi1:
|
|
return true;
|
|
}
|
|
}
|
|
|
|
bool HexagonMCInstrInfo::isVector(MCInstrInfo const &MCII, MCInst const &MCI) {
|
|
if ((getType(MCII, MCI) <= HexagonII::TypeCVI_LAST) &&
|
|
(getType(MCII, MCI) >= HexagonII::TypeCVI_FIRST))
|
|
return true;
|
|
return false;
|
|
}
|
|
|
|
int64_t HexagonMCInstrInfo::minConstant(MCInst const &MCI, size_t Index) {
|
|
auto Sentinal = static_cast<int64_t>(std::numeric_limits<uint32_t>::max())
|
|
<< 8;
|
|
if (MCI.size() <= Index)
|
|
return Sentinal;
|
|
MCOperand const &MCO = MCI.getOperand(Index);
|
|
if (!MCO.isExpr())
|
|
return Sentinal;
|
|
int64_t Value;
|
|
if (!MCO.getExpr()->evaluateAsAbsolute(Value))
|
|
return Sentinal;
|
|
return Value;
|
|
}
|
|
|
|
void HexagonMCInstrInfo::setMustExtend(MCExpr const &Expr, bool Val) {
|
|
HexagonMCExpr &HExpr = const_cast<HexagonMCExpr &>(cast<HexagonMCExpr>(Expr));
|
|
HExpr.setMustExtend(Val);
|
|
}
|
|
|
|
bool HexagonMCInstrInfo::mustExtend(MCExpr const &Expr) {
|
|
HexagonMCExpr const &HExpr = cast<HexagonMCExpr>(Expr);
|
|
return HExpr.mustExtend();
|
|
}
|
|
void HexagonMCInstrInfo::setMustNotExtend(MCExpr const &Expr, bool Val) {
|
|
HexagonMCExpr &HExpr = const_cast<HexagonMCExpr &>(cast<HexagonMCExpr>(Expr));
|
|
HExpr.setMustNotExtend(Val);
|
|
}
|
|
bool HexagonMCInstrInfo::mustNotExtend(MCExpr const &Expr) {
|
|
HexagonMCExpr const &HExpr = cast<HexagonMCExpr>(Expr);
|
|
return HExpr.mustNotExtend();
|
|
}
|
|
void HexagonMCInstrInfo::setS27_2_reloc(MCExpr const &Expr, bool Val) {
|
|
HexagonMCExpr &HExpr =
|
|
const_cast<HexagonMCExpr &>(*llvm::cast<HexagonMCExpr>(&Expr));
|
|
HExpr.setS27_2_reloc(Val);
|
|
}
|
|
bool HexagonMCInstrInfo::s27_2_reloc(MCExpr const &Expr) {
|
|
HexagonMCExpr const *HExpr = llvm::dyn_cast<HexagonMCExpr>(&Expr);
|
|
if (!HExpr)
|
|
return false;
|
|
return HExpr->s27_2_reloc();
|
|
}
|
|
|
|
void HexagonMCInstrInfo::padEndloop(MCInst &MCB, MCContext &Context) {
|
|
MCInst Nop;
|
|
Nop.setOpcode(Hexagon::A2_nop);
|
|
assert(isBundle(MCB));
|
|
while ((HexagonMCInstrInfo::isInnerLoop(MCB) &&
|
|
(HexagonMCInstrInfo::bundleSize(MCB) < HEXAGON_PACKET_INNER_SIZE)) ||
|
|
((HexagonMCInstrInfo::isOuterLoop(MCB) &&
|
|
(HexagonMCInstrInfo::bundleSize(MCB) < HEXAGON_PACKET_OUTER_SIZE))))
|
|
MCB.addOperand(MCOperand::createInst(new (Context) MCInst(Nop)));
|
|
}
|
|
|
|
bool HexagonMCInstrInfo::prefersSlot3(MCInstrInfo const &MCII,
|
|
MCInst const &MCI) {
|
|
const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
|
|
return (F >> HexagonII::PrefersSlot3Pos) & HexagonII::PrefersSlot3Mask;
|
|
}
|
|
|
|
void HexagonMCInstrInfo::replaceDuplex(MCContext &Context, MCInst &MCB,
|
|
DuplexCandidate Candidate) {
|
|
assert(Candidate.packetIndexI < MCB.size());
|
|
assert(Candidate.packetIndexJ < MCB.size());
|
|
assert(isBundle(MCB));
|
|
MCInst *Duplex =
|
|
deriveDuplex(Context, Candidate.iClass,
|
|
*MCB.getOperand(Candidate.packetIndexJ).getInst(),
|
|
*MCB.getOperand(Candidate.packetIndexI).getInst());
|
|
assert(Duplex != nullptr);
|
|
MCB.getOperand(Candidate.packetIndexI).setInst(Duplex);
|
|
MCB.erase(MCB.begin() + Candidate.packetIndexJ);
|
|
}
|
|
|
|
void HexagonMCInstrInfo::setInnerLoop(MCInst &MCI) {
|
|
assert(isBundle(MCI));
|
|
MCOperand &Operand = MCI.getOperand(0);
|
|
Operand.setImm(Operand.getImm() | innerLoopMask);
|
|
}
|
|
|
|
void HexagonMCInstrInfo::setMemReorderDisabled(MCInst &MCI) {
|
|
assert(isBundle(MCI));
|
|
MCOperand &Operand = MCI.getOperand(0);
|
|
Operand.setImm(Operand.getImm() | memReorderDisabledMask);
|
|
assert(isMemReorderDisabled(MCI));
|
|
}
|
|
|
|
void HexagonMCInstrInfo::setMemStoreReorderEnabled(MCInst &MCI) {
|
|
assert(isBundle(MCI));
|
|
MCOperand &Operand = MCI.getOperand(0);
|
|
Operand.setImm(Operand.getImm() | memStoreReorderEnabledMask);
|
|
assert(isMemStoreReorderEnabled(MCI));
|
|
}
|
|
|
|
void HexagonMCInstrInfo::setOuterLoop(MCInst &MCI) {
|
|
assert(isBundle(MCI));
|
|
MCOperand &Operand = MCI.getOperand(0);
|
|
Operand.setImm(Operand.getImm() | outerLoopMask);
|
|
}
|
|
|
|
unsigned HexagonMCInstrInfo::SubregisterBit(unsigned Consumer,
|
|
unsigned Producer,
|
|
unsigned Producer2) {
|
|
// If we're a single vector consumer of a double producer, set subreg bit
|
|
// based on if we're accessing the lower or upper register component
|
|
if (Producer >= Hexagon::W0 && Producer <= Hexagon::W15)
|
|
if (Consumer >= Hexagon::V0 && Consumer <= Hexagon::V31)
|
|
return (Consumer - Hexagon::V0) & 0x1;
|
|
if (Consumer == Producer2)
|
|
return 0x1;
|
|
return 0;
|
|
}
|
|
} // namespace llvm
|