forked from OSchip/llvm-project
563 lines
17 KiB
C++
563 lines
17 KiB
C++
//===-- AVRISelDAGToDAG.cpp - A dag to dag inst selector for AVR ----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines an instruction selector for the AVR target.
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//
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//===----------------------------------------------------------------------===//
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#include "AVR.h"
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#include "AVRTargetMachine.h"
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#include "MCTargetDesc/AVRMCTargetDesc.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#define DEBUG_TYPE "avr-isel"
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namespace llvm {
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/// Lowers LLVM IR (in DAG form) to AVR MC instructions (in DAG form).
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class AVRDAGToDAGISel : public SelectionDAGISel {
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public:
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AVRDAGToDAGISel(AVRTargetMachine &TM, CodeGenOpt::Level OptLevel)
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: SelectionDAGISel(TM, OptLevel), Subtarget(nullptr) {}
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StringRef getPassName() const override {
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return "AVR DAG->DAG Instruction Selection";
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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bool SelectAddr(SDNode *Op, SDValue N, SDValue &Base, SDValue &Disp);
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bool selectIndexedLoad(SDNode *N);
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unsigned selectIndexedProgMemLoad(const LoadSDNode *LD, MVT VT);
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bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintCode,
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std::vector<SDValue> &OutOps) override;
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// Include the pieces autogenerated from the target description.
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#include "AVRGenDAGISel.inc"
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private:
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void Select(SDNode *N) override;
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bool trySelect(SDNode *N);
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template <unsigned NodeType> bool select(SDNode *N);
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bool selectMultiplication(SDNode *N);
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const AVRSubtarget *Subtarget;
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};
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bool AVRDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
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Subtarget = &MF.getSubtarget<AVRSubtarget>();
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return SelectionDAGISel::runOnMachineFunction(MF);
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}
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bool AVRDAGToDAGISel::SelectAddr(SDNode *Op, SDValue N, SDValue &Base,
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SDValue &Disp) {
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SDLoc dl(Op);
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auto DL = CurDAG->getDataLayout();
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MVT PtrVT = getTargetLowering()->getPointerTy(DL);
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// if the address is a frame index get the TargetFrameIndex.
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if (const FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(N)) {
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Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), PtrVT);
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Disp = CurDAG->getTargetConstant(0, dl, MVT::i8);
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return true;
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}
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// Match simple Reg + uimm6 operands.
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if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
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!CurDAG->isBaseWithConstantOffset(N)) {
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return false;
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}
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if (const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
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int RHSC = (int)RHS->getZExtValue();
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// Convert negative offsets into positives ones.
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if (N.getOpcode() == ISD::SUB) {
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RHSC = -RHSC;
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}
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// <#Frame index + const>
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// Allow folding offsets bigger than 63 so the frame pointer can be used
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// directly instead of copying it around by adjusting and restoring it for
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// each access.
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if (N.getOperand(0).getOpcode() == ISD::FrameIndex) {
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int FI = cast<FrameIndexSDNode>(N.getOperand(0))->getIndex();
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Base = CurDAG->getTargetFrameIndex(FI, PtrVT);
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Disp = CurDAG->getTargetConstant(RHSC, dl, MVT::i16);
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return true;
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}
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// The value type of the memory instruction determines what is the maximum
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// offset allowed.
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MVT VT = cast<MemSDNode>(Op)->getMemoryVT().getSimpleVT();
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// We only accept offsets that fit in 6 bits (unsigned).
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if (isUInt<6>(RHSC) && (VT == MVT::i8 || VT == MVT::i16)) {
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Base = N.getOperand(0);
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Disp = CurDAG->getTargetConstant(RHSC, dl, MVT::i8);
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return true;
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}
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}
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return false;
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}
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bool AVRDAGToDAGISel::selectIndexedLoad(SDNode *N) {
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const LoadSDNode *LD = cast<LoadSDNode>(N);
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ISD::MemIndexedMode AM = LD->getAddressingMode();
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MVT VT = LD->getMemoryVT().getSimpleVT();
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auto PtrVT = getTargetLowering()->getPointerTy(CurDAG->getDataLayout());
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// We only care if this load uses a POSTINC or PREDEC mode.
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if ((LD->getExtensionType() != ISD::NON_EXTLOAD) ||
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(AM != ISD::POST_INC && AM != ISD::PRE_DEC)) {
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return false;
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}
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unsigned Opcode = 0;
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bool isPre = (AM == ISD::PRE_DEC);
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int Offs = cast<ConstantSDNode>(LD->getOffset())->getSExtValue();
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switch (VT.SimpleTy) {
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case MVT::i8: {
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if ((!isPre && Offs != 1) || (isPre && Offs != -1)) {
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return false;
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}
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Opcode = (isPre) ? AVR::LDRdPtrPd : AVR::LDRdPtrPi;
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break;
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}
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case MVT::i16: {
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if ((!isPre && Offs != 2) || (isPre && Offs != -2)) {
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return false;
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}
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Opcode = (isPre) ? AVR::LDWRdPtrPd : AVR::LDWRdPtrPi;
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break;
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}
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default:
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return false;
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}
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SDNode *ResNode = CurDAG->getMachineNode(Opcode, SDLoc(N), VT,
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PtrVT, MVT::Other,
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LD->getBasePtr(), LD->getChain());
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ReplaceUses(N, ResNode);
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CurDAG->RemoveDeadNode(N);
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return true;
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}
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unsigned AVRDAGToDAGISel::selectIndexedProgMemLoad(const LoadSDNode *LD,
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MVT VT) {
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ISD::MemIndexedMode AM = LD->getAddressingMode();
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// Progmem indexed loads only work in POSTINC mode.
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if (LD->getExtensionType() != ISD::NON_EXTLOAD || AM != ISD::POST_INC) {
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return 0;
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}
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unsigned Opcode = 0;
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int Offs = cast<ConstantSDNode>(LD->getOffset())->getSExtValue();
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switch (VT.SimpleTy) {
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case MVT::i8: {
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if (Offs != 1) {
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return 0;
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}
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Opcode = AVR::LPMRdZPi;
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break;
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}
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case MVT::i16: {
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if (Offs != 2) {
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return 0;
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}
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Opcode = AVR::LPMWRdZPi;
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break;
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}
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default:
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return 0;
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}
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return Opcode;
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}
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bool AVRDAGToDAGISel::SelectInlineAsmMemoryOperand(const SDValue &Op,
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unsigned ConstraintCode,
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std::vector<SDValue> &OutOps) {
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// Yes hardcoded 'm' symbol. Just because it also has been hardcoded in
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// SelectionDAGISel (callee for this method).
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assert(ConstraintCode == 'm' && "Unexpected asm memory constraint");
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MachineRegisterInfo &RI = MF->getRegInfo();
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const AVRSubtarget &STI = MF->getSubtarget<AVRSubtarget>();
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const TargetLowering &TL = *STI.getTargetLowering();
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SDLoc dl(Op);
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auto DL = CurDAG->getDataLayout();
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const RegisterSDNode *RegNode = dyn_cast<RegisterSDNode>(Op);
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// If address operand is of PTRDISPREGS class, all is OK, then.
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if (RegNode &&
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RI.getRegClass(RegNode->getReg()) == &AVR::PTRDISPREGSRegClass) {
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OutOps.push_back(Op);
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return false;
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}
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if (Op->getOpcode() == ISD::FrameIndex) {
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SDValue Base, Disp;
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if (SelectAddr(Op.getNode(), Op, Base, Disp)) {
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OutOps.push_back(Base);
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OutOps.push_back(Disp);
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return false;
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}
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return true;
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}
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// If Op is add 'register, immediate' and
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// register is either virtual register or register of PTRDISPREGSRegClass
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if (Op->getOpcode() == ISD::ADD || Op->getOpcode() == ISD::SUB) {
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SDValue CopyFromRegOp = Op->getOperand(0);
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SDValue ImmOp = Op->getOperand(1);
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ConstantSDNode *ImmNode = dyn_cast<ConstantSDNode>(ImmOp);
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unsigned Reg;
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bool CanHandleRegImmOpt = true;
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CanHandleRegImmOpt &= ImmNode != 0;
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CanHandleRegImmOpt &= ImmNode->getAPIntValue().getZExtValue() < 64;
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if (CopyFromRegOp->getOpcode() == ISD::CopyFromReg) {
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RegisterSDNode *RegNode =
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cast<RegisterSDNode>(CopyFromRegOp->getOperand(1));
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Reg = RegNode->getReg();
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CanHandleRegImmOpt &= (TargetRegisterInfo::isVirtualRegister(Reg) ||
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AVR::PTRDISPREGSRegClass.contains(Reg));
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} else {
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CanHandleRegImmOpt = false;
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}
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// If we detect proper case - correct virtual register class
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// if needed and go to another inlineasm operand.
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if (CanHandleRegImmOpt) {
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SDValue Base, Disp;
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if (RI.getRegClass(Reg) != &AVR::PTRDISPREGSRegClass) {
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SDLoc dl(CopyFromRegOp);
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unsigned VReg = RI.createVirtualRegister(&AVR::PTRDISPREGSRegClass);
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SDValue CopyToReg =
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CurDAG->getCopyToReg(CopyFromRegOp, dl, VReg, CopyFromRegOp);
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SDValue NewCopyFromRegOp =
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CurDAG->getCopyFromReg(CopyToReg, dl, VReg, TL.getPointerTy(DL));
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Base = NewCopyFromRegOp;
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} else {
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Base = CopyFromRegOp;
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}
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if (ImmNode->getValueType(0) != MVT::i8) {
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Disp = CurDAG->getTargetConstant(ImmNode->getAPIntValue().getZExtValue(), dl, MVT::i8);
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} else {
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Disp = ImmOp;
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}
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OutOps.push_back(Base);
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OutOps.push_back(Disp);
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return false;
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}
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}
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// More generic case.
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// Create chain that puts Op into pointer register
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// and return that register.
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unsigned VReg = RI.createVirtualRegister(&AVR::PTRDISPREGSRegClass);
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SDValue CopyToReg = CurDAG->getCopyToReg(Op, dl, VReg, Op);
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SDValue CopyFromReg =
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CurDAG->getCopyFromReg(CopyToReg, dl, VReg, TL.getPointerTy(DL));
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OutOps.push_back(CopyFromReg);
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return false;
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}
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template <> bool AVRDAGToDAGISel::select<ISD::FrameIndex>(SDNode *N) {
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auto DL = CurDAG->getDataLayout();
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// Convert the frameindex into a temp instruction that will hold the
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// effective address of the final stack slot.
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int FI = cast<FrameIndexSDNode>(N)->getIndex();
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SDValue TFI =
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CurDAG->getTargetFrameIndex(FI, getTargetLowering()->getPointerTy(DL));
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CurDAG->SelectNodeTo(N, AVR::FRMIDX,
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getTargetLowering()->getPointerTy(DL), TFI,
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CurDAG->getTargetConstant(0, SDLoc(N), MVT::i16));
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return true;
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}
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template <> bool AVRDAGToDAGISel::select<ISD::STORE>(SDNode *N) {
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// Use the STD{W}SPQRr pseudo instruction when passing arguments through
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// the stack on function calls for further expansion during the PEI phase.
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const StoreSDNode *ST = cast<StoreSDNode>(N);
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SDValue BasePtr = ST->getBasePtr();
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// Early exit when the base pointer is a frame index node or a constant.
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if (isa<FrameIndexSDNode>(BasePtr) || isa<ConstantSDNode>(BasePtr)) {
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return false;
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}
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const RegisterSDNode *RN = dyn_cast<RegisterSDNode>(BasePtr.getOperand(0));
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// Only stores where SP is the base pointer are valid.
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if (!RN || (RN->getReg() != AVR::SP)) {
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return false;
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}
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int CST = (int)cast<ConstantSDNode>(BasePtr.getOperand(1))->getZExtValue();
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SDValue Chain = ST->getChain();
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EVT VT = ST->getValue().getValueType();
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SDLoc DL(N);
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SDValue Offset = CurDAG->getTargetConstant(CST, DL, MVT::i16);
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SDValue Ops[] = {BasePtr.getOperand(0), Offset, ST->getValue(), Chain};
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unsigned Opc = (VT == MVT::i16) ? AVR::STDWSPQRr : AVR::STDSPQRr;
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SDNode *ResNode = CurDAG->getMachineNode(Opc, DL, MVT::Other, Ops);
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// Transfer memory operands.
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MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
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MemOp[0] = ST->getMemOperand();
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cast<MachineSDNode>(ResNode)->setMemRefs(MemOp, MemOp + 1);
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ReplaceUses(SDValue(N, 0), SDValue(ResNode, 0));
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CurDAG->RemoveDeadNode(N);
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return true;
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}
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template <> bool AVRDAGToDAGISel::select<ISD::LOAD>(SDNode *N) {
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const LoadSDNode *LD = cast<LoadSDNode>(N);
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if (!AVR::isProgramMemoryAccess(LD)) {
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// Check if the opcode can be converted into an indexed load.
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return selectIndexedLoad(N);
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}
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// This is a flash memory load, move the pointer into R31R30 and emit
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// the lpm instruction.
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MVT VT = LD->getMemoryVT().getSimpleVT();
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SDValue Chain = LD->getChain();
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SDValue Ptr = LD->getBasePtr();
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SDNode *ResNode;
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SDLoc DL(N);
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Chain = CurDAG->getCopyToReg(Chain, DL, AVR::R31R30, Ptr, SDValue());
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Ptr = CurDAG->getCopyFromReg(Chain, DL, AVR::R31R30, MVT::i16,
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Chain.getValue(1));
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SDValue RegZ = CurDAG->getRegister(AVR::R31R30, MVT::i16);
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// Check if the opcode can be converted into an indexed load.
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if (unsigned LPMOpc = selectIndexedProgMemLoad(LD, VT)) {
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// It is legal to fold the load into an indexed load.
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ResNode = CurDAG->getMachineNode(LPMOpc, DL, VT, MVT::i16, MVT::Other, Ptr,
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RegZ);
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ReplaceUses(SDValue(N, 1), SDValue(ResNode, 1));
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} else {
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// Selecting an indexed load is not legal, fallback to a normal load.
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switch (VT.SimpleTy) {
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case MVT::i8:
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ResNode = CurDAG->getMachineNode(AVR::LPMRdZ, DL, MVT::i8, MVT::Other,
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Ptr, RegZ);
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break;
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case MVT::i16:
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ResNode = CurDAG->getMachineNode(AVR::LPMWRdZ, DL, MVT::i16,
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MVT::Other, Ptr, RegZ);
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ReplaceUses(SDValue(N, 1), SDValue(ResNode, 1));
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break;
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default:
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llvm_unreachable("Unsupported VT!");
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}
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}
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// Transfer memory operands.
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MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
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MemOp[0] = LD->getMemOperand();
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cast<MachineSDNode>(ResNode)->setMemRefs(MemOp, MemOp + 1);
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ReplaceUses(SDValue(N, 0), SDValue(ResNode, 0));
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ReplaceUses(SDValue(N, 1), SDValue(ResNode, 1));
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CurDAG->RemoveDeadNode(N);
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return true;
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}
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template <> bool AVRDAGToDAGISel::select<AVRISD::CALL>(SDNode *N) {
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SDValue InFlag;
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SDValue Chain = N->getOperand(0);
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SDValue Callee = N->getOperand(1);
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unsigned LastOpNum = N->getNumOperands() - 1;
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// Direct calls are autogenerated.
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unsigned Op = Callee.getOpcode();
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if (Op == ISD::TargetGlobalAddress || Op == ISD::TargetExternalSymbol) {
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return false;
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}
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// Skip the incoming flag if present
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if (N->getOperand(LastOpNum).getValueType() == MVT::Glue) {
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--LastOpNum;
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}
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SDLoc DL(N);
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Chain = CurDAG->getCopyToReg(Chain, DL, AVR::R31R30, Callee, InFlag);
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SmallVector<SDValue, 8> Ops;
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Ops.push_back(CurDAG->getRegister(AVR::R31R30, MVT::i16));
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// Map all operands into the new node.
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for (unsigned i = 2, e = LastOpNum + 1; i != e; ++i) {
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Ops.push_back(N->getOperand(i));
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}
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Ops.push_back(Chain);
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Ops.push_back(Chain.getValue(1));
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SDNode *ResNode =
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CurDAG->getMachineNode(AVR::ICALL, DL, MVT::Other, MVT::Glue, Ops);
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ReplaceUses(SDValue(N, 0), SDValue(ResNode, 0));
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ReplaceUses(SDValue(N, 1), SDValue(ResNode, 1));
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CurDAG->RemoveDeadNode(N);
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return true;
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}
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template <> bool AVRDAGToDAGISel::select<ISD::BRIND>(SDNode *N) {
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SDValue Chain = N->getOperand(0);
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SDValue JmpAddr = N->getOperand(1);
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SDLoc DL(N);
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// Move the destination address of the indirect branch into R31R30.
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Chain = CurDAG->getCopyToReg(Chain, DL, AVR::R31R30, JmpAddr);
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SDNode *ResNode = CurDAG->getMachineNode(AVR::IJMP, DL, MVT::Other, Chain);
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ReplaceUses(SDValue(N, 0), SDValue(ResNode, 0));
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CurDAG->RemoveDeadNode(N);
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return true;
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}
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bool AVRDAGToDAGISel::selectMultiplication(llvm::SDNode *N) {
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SDLoc DL(N);
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MVT Type = N->getSimpleValueType(0);
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assert(Type == MVT::i8 && "unexpected value type");
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bool isSigned = N->getOpcode() == ISD::SMUL_LOHI;
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unsigned MachineOp = isSigned ? AVR::MULSRdRr : AVR::MULRdRr;
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SDValue Lhs = N->getOperand(0);
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SDValue Rhs = N->getOperand(1);
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SDNode *Mul = CurDAG->getMachineNode(MachineOp, DL, MVT::Glue, Lhs, Rhs);
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SDValue InChain = CurDAG->getEntryNode();
|
|
SDValue InGlue = SDValue(Mul, 0);
|
|
|
|
// Copy the low half of the result, if it is needed.
|
|
if (N->hasAnyUseOfValue(0)) {
|
|
SDValue CopyFromLo =
|
|
CurDAG->getCopyFromReg(InChain, DL, AVR::R0, Type, InGlue);
|
|
|
|
ReplaceUses(SDValue(N, 0), CopyFromLo);
|
|
|
|
InChain = CopyFromLo.getValue(1);
|
|
InGlue = CopyFromLo.getValue(2);
|
|
}
|
|
|
|
// Copy the high half of the result, if it is needed.
|
|
if (N->hasAnyUseOfValue(1)) {
|
|
SDValue CopyFromHi =
|
|
CurDAG->getCopyFromReg(InChain, DL, AVR::R1, Type, InGlue);
|
|
|
|
ReplaceUses(SDValue(N, 1), CopyFromHi);
|
|
|
|
InChain = CopyFromHi.getValue(1);
|
|
InGlue = CopyFromHi.getValue(2);
|
|
}
|
|
|
|
CurDAG->RemoveDeadNode(N);
|
|
|
|
// We need to clear R1. This is currently done (dirtily)
|
|
// using a custom inserter.
|
|
|
|
return true;
|
|
}
|
|
|
|
void AVRDAGToDAGISel::Select(SDNode *N) {
|
|
// Dump information about the Node being selected
|
|
DEBUG(errs() << "Selecting: "; N->dump(CurDAG); errs() << "\n");
|
|
|
|
// If we have a custom node, we already have selected!
|
|
if (N->isMachineOpcode()) {
|
|
DEBUG(errs() << "== "; N->dump(CurDAG); errs() << "\n");
|
|
N->setNodeId(-1);
|
|
return;
|
|
}
|
|
|
|
// See if subclasses can handle this node.
|
|
if (trySelect(N))
|
|
return;
|
|
|
|
// Select the default instruction
|
|
SelectCode(N);
|
|
}
|
|
|
|
bool AVRDAGToDAGISel::trySelect(SDNode *N) {
|
|
unsigned Opcode = N->getOpcode();
|
|
SDLoc DL(N);
|
|
|
|
switch (Opcode) {
|
|
// Nodes we fully handle.
|
|
case ISD::FrameIndex: return select<ISD::FrameIndex>(N);
|
|
case ISD::BRIND: return select<ISD::BRIND>(N);
|
|
case ISD::UMUL_LOHI:
|
|
case ISD::SMUL_LOHI: return selectMultiplication(N);
|
|
|
|
// Nodes we handle partially. Other cases are autogenerated
|
|
case ISD::STORE: return select<ISD::STORE>(N);
|
|
case ISD::LOAD: return select<ISD::LOAD>(N);
|
|
case AVRISD::CALL: return select<AVRISD::CALL>(N);
|
|
default: return false;
|
|
}
|
|
}
|
|
|
|
FunctionPass *createAVRISelDag(AVRTargetMachine &TM,
|
|
CodeGenOpt::Level OptLevel) {
|
|
return new AVRDAGToDAGISel(TM, OptLevel);
|
|
}
|
|
|
|
} // end of namespace llvm
|
|
|