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llvm-project/llvm/lib/Target/RISCV
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Alex Bradbury 8bba6bfeef [RISCV] MC layer support for the instructions added in the privileged spec 
Adds support for the instructions added in the RISC-V privileged ISA
(https://content.riscv.org/wp-content/uploads/2017/05/riscv-privileged-v1.10.pdf):
uret, sret, mret, wfi, and sfence.vma.

Note from the committer: I made very minor formatting changes prior to commit, 
which didn't seem worth creating another review round-trip for.

Differential Revision: https://reviews.llvm.org/D40383

Patch by David Craven.

llvm-svn: 320484
 		2017-12-12 15:17:45 +00:00
..
AsmParser [RISCV] MC layer support for the jump/branch instructions of the RVC extension 2017-12-07 13:19:57 +00:00
Disassembler [RISCV] MC layer support for load/store instructions of the C (compressed) extension 2017-12-07 12:50:32 +00:00
InstPrinter [RISCV] MC layer support for the standard RV32F instruction set extension 2017-12-07 10:26:05 +00:00
MCTargetDesc [RISCV] MC layer support for the jump/branch instructions of the RVC extension 2017-12-07 13:19:57 +00:00
TargetInfo Fix RISCV build after r318352 2017-11-16 18:39:31 +00:00
CMakeLists.txt [RISCV] Add custom CC_RISCV calling convention and improved call support 2017-12-11 12:49:02 +00:00
LLVMBuild.txt [RISCV] Initial codegen support for ALU operations 2017-10-19 21:37:38 +00:00
RISCV.h [RISCV] Codegen support for memory operations on global addresses 2017-11-08 13:24:21 +00:00
RISCV.td [RISCV] MC layer support for load/store instructions of the C (compressed) extension 2017-12-07 12:50:32 +00:00
RISCVAsmPrinter.cpp [RISCV] Codegen support for memory operations on global addresses 2017-11-08 13:24:21 +00:00
RISCVCallingConv.td [RISCV] Add custom CC_RISCV calling convention and improved call support 2017-12-11 12:49:02 +00:00
RISCVFrameLowering.cpp [RISCV] Implement prolog and epilog insertion 2017-12-11 12:34:11 +00:00
RISCVFrameLowering.h [RISCV] Implement prolog and epilog insertion 2017-12-11 12:34:11 +00:00
RISCVISelDAGToDAG.cpp [RISCV] Support lowering FrameIndex 2017-12-11 11:53:54 +00:00
RISCVISelLowering.cpp [RISCV] Add custom CC_RISCV calling convention and improved call support 2017-12-11 12:49:02 +00:00
RISCVISelLowering.h [RISCV] Add custom CC_RISCV calling convention and improved call support 2017-12-11 12:49:02 +00:00
RISCVInstrFormats.td [RISCV] MC layer support for load/store instructions of the C (compressed) extension 2017-12-07 12:50:32 +00:00
RISCVInstrFormatsC.td [RISCV] MC layer support for the jump/branch instructions of the RVC extension 2017-12-07 13:19:57 +00:00
RISCVInstrInfo.cpp [RISCV][NFC] Use TargetRegisterClass::hasSubClassEq in storeRegToStackSlot/loadReadFromStackSlot 2017-12-07 12:45:05 +00:00
RISCVInstrInfo.h [RISCV] Codegen for conditional branches 2017-11-08 13:31:40 +00:00
RISCVInstrInfo.td [RISCV] MC layer support for the instructions added in the privileged spec 2017-12-12 15:17:45 +00:00
RISCVInstrInfoA.td [RISCV] MC layer support for the standard RV64A instruction set extension 2017-12-07 10:59:12 +00:00
RISCVInstrInfoC.td [RISCV] MC layer support for the jump/branch instructions of the RVC extension 2017-12-07 13:19:57 +00:00
RISCVInstrInfoD.td [RISCV] MC layer support for the standard RV64D instruction set extension 2017-12-07 11:04:18 +00:00
RISCVInstrInfoF.td [RISCV] MC layer support for the standard RV64F instruction set extension 2017-12-07 11:02:55 +00:00
RISCVInstrInfoM.td [RISCV] MC layer support for the standard RV64M instruction set extension 2017-12-07 10:56:07 +00:00
RISCVMCInstLower.cpp [RISCV] Support and tests for a variety of additional LLVM IR constructs 2017-11-21 08:11:03 +00:00
RISCVRegisterInfo.cpp [RISCV] Support lowering FrameIndex 2017-12-11 11:53:54 +00:00
RISCVRegisterInfo.h Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
RISCVRegisterInfo.td [RISCV] MC layer support for load/store instructions of the C (compressed) extension 2017-12-07 12:50:32 +00:00
RISCVSubtarget.cpp [RISCV] Initial codegen support for ALU operations 2017-10-19 21:37:38 +00:00
RISCVSubtarget.h [RISCV] MC layer support for load/store instructions of the C (compressed) extension 2017-12-07 12:50:32 +00:00
RISCVTargetMachine.cpp [RISCV] Fix 64-bit data layout mismatch between backend and target description 2017-11-16 20:30:49 +00:00
RISCVTargetMachine.h [RISCV] Initial codegen support for ALU operations 2017-10-19 21:37:38 +00:00