llvm-project/llvm/test/MC/Disassembler
Dmitry Preobrazhensky 4c45e6ff0e [AMDGPU][MC][VI][GFX9] Added support of SDWA/DPP for v_cndmask_b32
See bug 36356: https://bugs.llvm.org/show_bug.cgi?id=36356

Differential Revision: https://reviews.llvm.org/D45446

Reviewers: artem.tamazov, arsenm, timcorringham
llvm-svn: 330123
2018-04-16 12:41:38 +00:00
..
AArch64 [AArch64] Fix spelling of ICH_ELRSR_EL2 system register 2018-02-06 09:39:04 +00:00
AMDGPU [AMDGPU][MC][VI][GFX9] Added support of SDWA/DPP for v_cndmask_b32 2018-04-16 12:41:38 +00:00
ARC [ARC] Add LImm support for J/JL 2018-04-13 15:10:34 +00:00
ARM [ARM]Decoding MSR with unpredictable destination register causes an assert 2018-03-06 15:21:19 +00:00
Hexagon [Hexagon] Remove trailing spaces, NFC 2017-11-22 20:43:00 +00:00
Lanai
Mips [mips] Correct the predicates for special nops, tlb ctrl instrs, software breakpoint and prefx. 2018-04-12 12:37:02 +00:00
PowerPC [PowerPC] Code cleanup. Remove instructions that were withdrawn from Power 9. 2018-02-23 15:55:16 +00:00
Sparc
SystemZ [SystemZ] Add support for IBM z14 processor (3/3) 2017-07-17 17:44:20 +00:00
X86 [X86] Add the bizarro movsww and movzww mnemonics for the disassembler. 2018-04-13 23:57:54 +00:00
XCore