forked from OSchip/llvm-project
566 lines
18 KiB
LLVM
566 lines
18 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=SSE --check-prefix=SSE2
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE --check-prefix=SSE41
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX --check-prefix=AVX1
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX --check-prefix=AVX2
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; Verify that we don't emit packed vector shifts instructions if the
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; condition used by the vector select is a vector of constants.
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define <4 x float> @test1(<4 x float> %a, <4 x float> %b) {
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; SSE2-LABEL: test1:
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; SSE2: # %bb.0:
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; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
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; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
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; SSE2-NEXT: retq
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;
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; SSE41-LABEL: test1:
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; SSE41: # %bb.0:
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; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: test1:
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; AVX: # %bb.0:
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; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
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; AVX-NEXT: retq
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%1 = select <4 x i1> <i1 true, i1 false, i1 true, i1 false>, <4 x float> %a, <4 x float> %b
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ret <4 x float> %1
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}
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define <4 x float> @test2(<4 x float> %a, <4 x float> %b) {
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; SSE2-LABEL: test2:
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; SSE2: # %bb.0:
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; SSE2-NEXT: movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
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; SSE2-NEXT: movapd %xmm1, %xmm0
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; SSE2-NEXT: retq
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;
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; SSE41-LABEL: test2:
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; SSE41: # %bb.0:
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; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: test2:
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; AVX: # %bb.0:
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; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]
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; AVX-NEXT: retq
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%1 = select <4 x i1> <i1 true, i1 true, i1 false, i1 false>, <4 x float> %a, <4 x float> %b
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ret <4 x float> %1
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}
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define <4 x float> @test3(<4 x float> %a, <4 x float> %b) {
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; SSE2-LABEL: test3:
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; SSE2: # %bb.0:
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; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
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; SSE2-NEXT: retq
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;
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; SSE41-LABEL: test3:
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; SSE41: # %bb.0:
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; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3]
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: test3:
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; AVX: # %bb.0:
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; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3]
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; AVX-NEXT: retq
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%1 = select <4 x i1> <i1 false, i1 false, i1 true, i1 true>, <4 x float> %a, <4 x float> %b
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ret <4 x float> %1
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}
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define <4 x float> @test4(<4 x float> %a, <4 x float> %b) {
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; SSE-LABEL: test4:
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; SSE: # %bb.0:
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; SSE-NEXT: movaps %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: test4:
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; AVX: # %bb.0:
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; AVX-NEXT: vmovaps %xmm1, %xmm0
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; AVX-NEXT: retq
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%1 = select <4 x i1> <i1 false, i1 false, i1 false, i1 false>, <4 x float> %a, <4 x float> %b
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ret <4 x float> %1
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}
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define <4 x float> @test5(<4 x float> %a, <4 x float> %b) {
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; SSE-LABEL: test5:
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; SSE: # %bb.0:
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; SSE-NEXT: retq
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;
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; AVX-LABEL: test5:
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; AVX: # %bb.0:
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; AVX-NEXT: retq
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%1 = select <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x float> %a, <4 x float> %b
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ret <4 x float> %1
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}
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define <8 x i16> @test6(<8 x i16> %a, <8 x i16> %b) {
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; SSE-LABEL: test6:
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; SSE: # %bb.0:
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; SSE-NEXT: retq
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;
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; AVX-LABEL: test6:
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; AVX: # %bb.0:
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; AVX-NEXT: retq
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%1 = select <8 x i1> <i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false>, <8 x i16> %a, <8 x i16> %a
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ret <8 x i16> %1
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}
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define <8 x i16> @test7(<8 x i16> %a, <8 x i16> %b) {
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; SSE2-LABEL: test7:
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; SSE2: # %bb.0:
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; SSE2-NEXT: movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
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; SSE2-NEXT: movapd %xmm1, %xmm0
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; SSE2-NEXT: retq
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;
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; SSE41-LABEL: test7:
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; SSE41: # %bb.0:
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; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: test7:
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; AVX: # %bb.0:
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; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]
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; AVX-NEXT: retq
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%1 = select <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false>, <8 x i16> %a, <8 x i16> %b
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ret <8 x i16> %1
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}
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define <8 x i16> @test8(<8 x i16> %a, <8 x i16> %b) {
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; SSE2-LABEL: test8:
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; SSE2: # %bb.0:
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; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
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; SSE2-NEXT: retq
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;
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; SSE41-LABEL: test8:
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; SSE41: # %bb.0:
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; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3]
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: test8:
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; AVX: # %bb.0:
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; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3]
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; AVX-NEXT: retq
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%1 = select <8 x i1> <i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true>, <8 x i16> %a, <8 x i16> %b
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ret <8 x i16> %1
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}
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define <8 x i16> @test9(<8 x i16> %a, <8 x i16> %b) {
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; SSE-LABEL: test9:
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; SSE: # %bb.0:
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; SSE-NEXT: movaps %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: test9:
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; AVX: # %bb.0:
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; AVX-NEXT: vmovaps %xmm1, %xmm0
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; AVX-NEXT: retq
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%1 = select <8 x i1> <i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>, <8 x i16> %a, <8 x i16> %b
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ret <8 x i16> %1
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}
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define <8 x i16> @test10(<8 x i16> %a, <8 x i16> %b) {
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; SSE-LABEL: test10:
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; SSE: # %bb.0:
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; SSE-NEXT: retq
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;
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; AVX-LABEL: test10:
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; AVX: # %bb.0:
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; AVX-NEXT: retq
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%1 = select <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <8 x i16> %a, <8 x i16> %b
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ret <8 x i16> %1
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}
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define <8 x i16> @test11(<8 x i16> %a, <8 x i16> %b) {
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; SSE2-LABEL: test11:
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; SSE2: # %bb.0:
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; SSE2-NEXT: movaps {{.*#+}} xmm2 = [0,65535,65535,0,0,65535,65535,0]
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; SSE2-NEXT: andps %xmm2, %xmm0
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; SSE2-NEXT: andnps %xmm1, %xmm2
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; SSE2-NEXT: orps %xmm2, %xmm0
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; SSE2-NEXT: retq
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;
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; SSE41-LABEL: test11:
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; SSE41: # %bb.0:
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; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0],xmm0[1,2],xmm1[3,4],xmm0[5,6],xmm1[7]
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: test11:
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; AVX: # %bb.0:
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; AVX-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0],xmm0[1,2],xmm1[3,4],xmm0[5,6],xmm1[7]
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; AVX-NEXT: retq
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%1 = select <8 x i1> <i1 false, i1 true, i1 true, i1 false, i1 undef, i1 true, i1 true, i1 undef>, <8 x i16> %a, <8 x i16> %b
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ret <8 x i16> %1
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}
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define <8 x i16> @test12(<8 x i16> %a, <8 x i16> %b) {
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; SSE-LABEL: test12:
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; SSE: # %bb.0:
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; SSE-NEXT: movaps %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: test12:
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; AVX: # %bb.0:
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; AVX-NEXT: vmovaps %xmm1, %xmm0
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; AVX-NEXT: retq
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%1 = select <8 x i1> <i1 false, i1 false, i1 undef, i1 false, i1 false, i1 false, i1 false, i1 undef>, <8 x i16> %a, <8 x i16> %b
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ret <8 x i16> %1
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}
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define <8 x i16> @test13(<8 x i16> %a, <8 x i16> %b) {
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; SSE-LABEL: test13:
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; SSE: # %bb.0:
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; SSE-NEXT: movaps %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: test13:
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; AVX: # %bb.0:
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; AVX-NEXT: vmovaps %xmm1, %xmm0
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; AVX-NEXT: retq
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%1 = select <8 x i1> <i1 undef, i1 undef, i1 undef, i1 undef, i1 undef, i1 undef, i1 undef, i1 undef>, <8 x i16> %a, <8 x i16> %b
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ret <8 x i16> %1
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}
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; Fold (vselect (build_vector AllOnes), N1, N2) -> N1
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define <4 x float> @test14(<4 x float> %a, <4 x float> %b) {
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; SSE-LABEL: test14:
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; SSE: # %bb.0:
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; SSE-NEXT: retq
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;
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; AVX-LABEL: test14:
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; AVX: # %bb.0:
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; AVX-NEXT: retq
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%1 = select <4 x i1> <i1 true, i1 undef, i1 true, i1 undef>, <4 x float> %a, <4 x float> %b
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ret <4 x float> %1
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}
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define <8 x i16> @test15(<8 x i16> %a, <8 x i16> %b) {
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; SSE-LABEL: test15:
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; SSE: # %bb.0:
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; SSE-NEXT: retq
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;
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; AVX-LABEL: test15:
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; AVX: # %bb.0:
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; AVX-NEXT: retq
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%1 = select <8 x i1> <i1 true, i1 true, i1 true, i1 undef, i1 undef, i1 true, i1 true, i1 undef>, <8 x i16> %a, <8 x i16> %b
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ret <8 x i16> %1
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}
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; Fold (vselect (build_vector AllZeros), N1, N2) -> N2
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define <4 x float> @test16(<4 x float> %a, <4 x float> %b) {
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; SSE-LABEL: test16:
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; SSE: # %bb.0:
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; SSE-NEXT: movaps %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: test16:
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; AVX: # %bb.0:
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; AVX-NEXT: vmovaps %xmm1, %xmm0
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; AVX-NEXT: retq
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%1 = select <4 x i1> <i1 false, i1 undef, i1 false, i1 undef>, <4 x float> %a, <4 x float> %b
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ret <4 x float> %1
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}
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define <8 x i16> @test17(<8 x i16> %a, <8 x i16> %b) {
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; SSE-LABEL: test17:
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; SSE: # %bb.0:
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; SSE-NEXT: movaps %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: test17:
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; AVX: # %bb.0:
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; AVX-NEXT: vmovaps %xmm1, %xmm0
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; AVX-NEXT: retq
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%1 = select <8 x i1> <i1 false, i1 false, i1 false, i1 undef, i1 undef, i1 false, i1 false, i1 undef>, <8 x i16> %a, <8 x i16> %b
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ret <8 x i16> %1
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}
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define <4 x float> @test18(<4 x float> %a, <4 x float> %b) {
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; SSE2-LABEL: test18:
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; SSE2: # %bb.0:
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; SSE2-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
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; SSE2-NEXT: retq
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;
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; SSE41-LABEL: test18:
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; SSE41: # %bb.0:
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; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: test18:
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; AVX: # %bb.0:
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; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
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; AVX-NEXT: retq
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%1 = select <4 x i1> <i1 false, i1 true, i1 true, i1 true>, <4 x float> %a, <4 x float> %b
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ret <4 x float> %1
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}
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define <4 x i32> @test19(<4 x i32> %a, <4 x i32> %b) {
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; SSE2-LABEL: test19:
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; SSE2: # %bb.0:
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; SSE2-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
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; SSE2-NEXT: retq
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;
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; SSE41-LABEL: test19:
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; SSE41: # %bb.0:
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; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: test19:
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; AVX: # %bb.0:
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; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
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; AVX-NEXT: retq
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%1 = select <4 x i1> <i1 false, i1 true, i1 true, i1 true>, <4 x i32> %a, <4 x i32> %b
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ret <4 x i32> %1
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}
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define <2 x double> @test20(<2 x double> %a, <2 x double> %b) {
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; SSE2-LABEL: test20:
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; SSE2: # %bb.0:
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; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
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; SSE2-NEXT: retq
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;
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; SSE41-LABEL: test20:
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; SSE41: # %bb.0:
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; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3]
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: test20:
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; AVX: # %bb.0:
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; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3]
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; AVX-NEXT: retq
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%1 = select <2 x i1> <i1 false, i1 true>, <2 x double> %a, <2 x double> %b
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ret <2 x double> %1
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}
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define <2 x i64> @test21(<2 x i64> %a, <2 x i64> %b) {
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; SSE2-LABEL: test21:
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; SSE2: # %bb.0:
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; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
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; SSE2-NEXT: retq
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;
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; SSE41-LABEL: test21:
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; SSE41: # %bb.0:
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; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3]
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: test21:
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; AVX: # %bb.0:
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; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3]
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; AVX-NEXT: retq
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%1 = select <2 x i1> <i1 false, i1 true>, <2 x i64> %a, <2 x i64> %b
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ret <2 x i64> %1
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}
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define <4 x float> @test22(<4 x float> %a, <4 x float> %b) {
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; SSE2-LABEL: test22:
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; SSE2: # %bb.0:
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; SSE2-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
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; SSE2-NEXT: movaps %xmm1, %xmm0
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; SSE2-NEXT: retq
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;
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; SSE41-LABEL: test22:
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; SSE41: # %bb.0:
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; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: test22:
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; AVX: # %bb.0:
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; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
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; AVX-NEXT: retq
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%1 = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x float> %a, <4 x float> %b
|
|
ret <4 x float> %1
|
|
}
|
|
|
|
define <4 x i32> @test23(<4 x i32> %a, <4 x i32> %b) {
|
|
; SSE2-LABEL: test23:
|
|
; SSE2: # %bb.0:
|
|
; SSE2-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
|
|
; SSE2-NEXT: movaps %xmm1, %xmm0
|
|
; SSE2-NEXT: retq
|
|
;
|
|
; SSE41-LABEL: test23:
|
|
; SSE41: # %bb.0:
|
|
; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
|
|
; SSE41-NEXT: retq
|
|
;
|
|
; AVX-LABEL: test23:
|
|
; AVX: # %bb.0:
|
|
; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
|
|
; AVX-NEXT: retq
|
|
%1 = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x i32> %a, <4 x i32> %b
|
|
ret <4 x i32> %1
|
|
}
|
|
|
|
define <2 x double> @test24(<2 x double> %a, <2 x double> %b) {
|
|
; SSE2-LABEL: test24:
|
|
; SSE2: # %bb.0:
|
|
; SSE2-NEXT: movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
|
|
; SSE2-NEXT: movapd %xmm1, %xmm0
|
|
; SSE2-NEXT: retq
|
|
;
|
|
; SSE41-LABEL: test24:
|
|
; SSE41: # %bb.0:
|
|
; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]
|
|
; SSE41-NEXT: retq
|
|
;
|
|
; AVX-LABEL: test24:
|
|
; AVX: # %bb.0:
|
|
; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]
|
|
; AVX-NEXT: retq
|
|
%1 = select <2 x i1> <i1 true, i1 false>, <2 x double> %a, <2 x double> %b
|
|
ret <2 x double> %1
|
|
}
|
|
|
|
define <2 x i64> @test25(<2 x i64> %a, <2 x i64> %b) {
|
|
; SSE2-LABEL: test25:
|
|
; SSE2: # %bb.0:
|
|
; SSE2-NEXT: movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
|
|
; SSE2-NEXT: movapd %xmm1, %xmm0
|
|
; SSE2-NEXT: retq
|
|
;
|
|
; SSE41-LABEL: test25:
|
|
; SSE41: # %bb.0:
|
|
; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]
|
|
; SSE41-NEXT: retq
|
|
;
|
|
; AVX-LABEL: test25:
|
|
; AVX: # %bb.0:
|
|
; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]
|
|
; AVX-NEXT: retq
|
|
%1 = select <2 x i1> <i1 true, i1 false>, <2 x i64> %a, <2 x i64> %b
|
|
ret <2 x i64> %1
|
|
}
|
|
|
|
define <4 x float> @select_of_shuffles_0(<2 x float> %a0, <2 x float> %b0, <2 x float> %a1, <2 x float> %b1) {
|
|
; SSE-LABEL: select_of_shuffles_0:
|
|
; SSE: # %bb.0:
|
|
; SSE-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0]
|
|
; SSE-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm3[0]
|
|
; SSE-NEXT: subps %xmm1, %xmm0
|
|
; SSE-NEXT: retq
|
|
;
|
|
; AVX-LABEL: select_of_shuffles_0:
|
|
; AVX: # %bb.0:
|
|
; AVX-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0]
|
|
; AVX-NEXT: vmovlhps {{.*#+}} xmm1 = xmm1[0],xmm3[0]
|
|
; AVX-NEXT: vsubps %xmm1, %xmm0, %xmm0
|
|
; AVX-NEXT: retq
|
|
%1 = shufflevector <2 x float> %a0, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
|
|
%2 = shufflevector <2 x float> %a1, <2 x float> undef, <4 x i32> <i32 undef, i32 undef, i32 0, i32 1>
|
|
%3 = select <4 x i1> <i1 false, i1 false, i1 true, i1 true>, <4 x float> %2, <4 x float> %1
|
|
%4 = shufflevector <2 x float> %b0, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
|
|
%5 = shufflevector <2 x float> %b1, <2 x float> undef, <4 x i32> <i32 undef, i32 undef, i32 0, i32 1>
|
|
%6 = select <4 x i1> <i1 false, i1 false, i1 true, i1 true>, <4 x float> %5, <4 x float> %4
|
|
%7 = fsub <4 x float> %3, %6
|
|
ret <4 x float> %7
|
|
}
|
|
|
|
; PR20677
|
|
define <16 x double> @select_illegal(<16 x double> %a, <16 x double> %b) {
|
|
; SSE-LABEL: select_illegal:
|
|
; SSE: # %bb.0:
|
|
; SSE-NEXT: movaps {{[0-9]+}}(%rsp), %xmm4
|
|
; SSE-NEXT: movaps {{[0-9]+}}(%rsp), %xmm5
|
|
; SSE-NEXT: movaps {{[0-9]+}}(%rsp), %xmm6
|
|
; SSE-NEXT: movaps {{[0-9]+}}(%rsp), %xmm7
|
|
; SSE-NEXT: movaps %xmm7, 112(%rdi)
|
|
; SSE-NEXT: movaps %xmm6, 96(%rdi)
|
|
; SSE-NEXT: movaps %xmm5, 80(%rdi)
|
|
; SSE-NEXT: movaps %xmm4, 64(%rdi)
|
|
; SSE-NEXT: movaps %xmm3, 48(%rdi)
|
|
; SSE-NEXT: movaps %xmm2, 32(%rdi)
|
|
; SSE-NEXT: movaps %xmm1, 16(%rdi)
|
|
; SSE-NEXT: movaps %xmm0, (%rdi)
|
|
; SSE-NEXT: movq %rdi, %rax
|
|
; SSE-NEXT: retq
|
|
;
|
|
; AVX-LABEL: select_illegal:
|
|
; AVX: # %bb.0:
|
|
; AVX-NEXT: vmovaps %ymm6, %ymm2
|
|
; AVX-NEXT: vmovaps %ymm7, %ymm3
|
|
; AVX-NEXT: retq
|
|
%sel = select <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>, <16 x double> %a, <16 x double> %b
|
|
ret <16 x double> %sel
|
|
}
|
|
|
|
; Make sure we can optimize the condition MSB when it is used by 2 selects.
|
|
; The v2i1 here will be passed as v2i64 and we will emit a sign_extend_inreg to fill the upper bits.
|
|
; We should be able to remove the sra from the sign_extend_inreg to leave only shl.
|
|
define <2 x i64> @shrunkblend_2uses(<2 x i1> %cond, <2 x i64> %a, <2 x i64> %b, <2 x i64> %c, <2 x i64> %d) {
|
|
; SSE2-LABEL: shrunkblend_2uses:
|
|
; SSE2: # %bb.0:
|
|
; SSE2-NEXT: psllq $63, %xmm0
|
|
; SSE2-NEXT: psrad $31, %xmm0
|
|
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
|
|
; SSE2-NEXT: movdqa %xmm0, %xmm5
|
|
; SSE2-NEXT: pandn %xmm2, %xmm5
|
|
; SSE2-NEXT: pand %xmm0, %xmm1
|
|
; SSE2-NEXT: por %xmm1, %xmm5
|
|
; SSE2-NEXT: pand %xmm0, %xmm3
|
|
; SSE2-NEXT: pandn %xmm4, %xmm0
|
|
; SSE2-NEXT: por %xmm3, %xmm0
|
|
; SSE2-NEXT: paddq %xmm5, %xmm0
|
|
; SSE2-NEXT: retq
|
|
;
|
|
; SSE41-LABEL: shrunkblend_2uses:
|
|
; SSE41: # %bb.0:
|
|
; SSE41-NEXT: psllq $63, %xmm0
|
|
; SSE41-NEXT: psrad $31, %xmm0
|
|
; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
|
|
; SSE41-NEXT: blendvpd %xmm0, %xmm1, %xmm2
|
|
; SSE41-NEXT: blendvpd %xmm0, %xmm3, %xmm4
|
|
; SSE41-NEXT: paddq %xmm2, %xmm4
|
|
; SSE41-NEXT: movdqa %xmm4, %xmm0
|
|
; SSE41-NEXT: retq
|
|
;
|
|
; AVX-LABEL: shrunkblend_2uses:
|
|
; AVX: # %bb.0:
|
|
; AVX-NEXT: vpsllq $63, %xmm0, %xmm0
|
|
; AVX-NEXT: vpxor %xmm5, %xmm5, %xmm5
|
|
; AVX-NEXT: vpcmpgtq %xmm0, %xmm5, %xmm0
|
|
; AVX-NEXT: vblendvpd %xmm0, %xmm1, %xmm2, %xmm1
|
|
; AVX-NEXT: vblendvpd %xmm0, %xmm3, %xmm4, %xmm0
|
|
; AVX-NEXT: vpaddq %xmm0, %xmm1, %xmm0
|
|
; AVX-NEXT: retq
|
|
%x = select <2 x i1> %cond, <2 x i64> %a, <2 x i64> %b
|
|
%y = select <2 x i1> %cond, <2 x i64> %c, <2 x i64> %d
|
|
%z = add <2 x i64> %x, %y
|
|
ret <2 x i64> %z
|
|
}
|
|
|
|
; Similar to above, but condition has a use that isn't a condition of a vselect so we can't optimize.
|
|
define <2 x i64> @shrunkblend_nonvselectuse(<2 x i1> %cond, <2 x i64> %a, <2 x i64> %b, <2 x i64> %c, <2 x i64> %d) {
|
|
; SSE2-LABEL: shrunkblend_nonvselectuse:
|
|
; SSE2: # %bb.0:
|
|
; SSE2-NEXT: psllq $63, %xmm0
|
|
; SSE2-NEXT: psrad $31, %xmm0
|
|
; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
|
|
; SSE2-NEXT: movdqa %xmm3, %xmm0
|
|
; SSE2-NEXT: pandn %xmm2, %xmm0
|
|
; SSE2-NEXT: pand %xmm3, %xmm1
|
|
; SSE2-NEXT: por %xmm1, %xmm0
|
|
; SSE2-NEXT: paddq %xmm3, %xmm0
|
|
; SSE2-NEXT: retq
|
|
;
|
|
; SSE41-LABEL: shrunkblend_nonvselectuse:
|
|
; SSE41: # %bb.0:
|
|
; SSE41-NEXT: psllq $63, %xmm0
|
|
; SSE41-NEXT: psrad $31, %xmm0
|
|
; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
|
|
; SSE41-NEXT: blendvpd %xmm0, %xmm1, %xmm2
|
|
; SSE41-NEXT: paddq %xmm2, %xmm0
|
|
; SSE41-NEXT: retq
|
|
;
|
|
; AVX-LABEL: shrunkblend_nonvselectuse:
|
|
; AVX: # %bb.0:
|
|
; AVX-NEXT: vpsllq $63, %xmm0, %xmm0
|
|
; AVX-NEXT: vpxor %xmm3, %xmm3, %xmm3
|
|
; AVX-NEXT: vpcmpgtq %xmm0, %xmm3, %xmm0
|
|
; AVX-NEXT: vblendvpd %xmm0, %xmm1, %xmm2, %xmm1
|
|
; AVX-NEXT: vpaddq %xmm0, %xmm1, %xmm0
|
|
; AVX-NEXT: retq
|
|
%x = select <2 x i1> %cond, <2 x i64> %a, <2 x i64> %b
|
|
%y = sext <2 x i1> %cond to <2 x i64>
|
|
%z = add <2 x i64> %x, %y
|
|
ret <2 x i64> %z
|
|
}
|
|
|