forked from OSchip/llvm-project
108 lines
4.5 KiB
C++
108 lines
4.5 KiB
C++
//===-- R600ISelLowering.h - R600 DAG Lowering Interface -*- C++ -*--------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief R600 DAG Lowering interface definition
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_R600ISELLOWERING_H
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#define LLVM_LIB_TARGET_AMDGPU_R600ISELLOWERING_H
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#include "AMDGPUISelLowering.h"
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namespace llvm {
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class R600InstrInfo;
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class R600Subtarget;
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class R600TargetLowering final : public AMDGPUTargetLowering {
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public:
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R600TargetLowering(const TargetMachine &TM, const R600Subtarget &STI);
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const R600Subtarget *getSubtarget() const;
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MachineBasicBlock *
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EmitInstrWithCustomInserter(MachineInstr &MI,
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MachineBasicBlock *BB) const override;
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SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
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SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
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void ReplaceNodeResults(SDNode * N,
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SmallVectorImpl<SDValue> &Results,
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SelectionDAG &DAG) const override;
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SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
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bool isVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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const SDLoc &DL, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const override;
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EVT getSetCCResultType(const DataLayout &DL, LLVMContext &,
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EVT VT) const override;
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bool canMergeStoresTo(unsigned AS, EVT MemVT,
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const SelectionDAG &DAG) const override;
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bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS,
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unsigned Align,
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bool *IsFast) const override;
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private:
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unsigned Gen;
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/// Each OpenCL kernel has nine implicit parameters that are stored in the
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/// first nine dwords of a Vertex Buffer. These implicit parameters are
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/// lowered to load instructions which retrieve the values from the Vertex
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/// Buffer.
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SDValue LowerImplicitParameter(SelectionDAG &DAG, EVT VT, const SDLoc &DL,
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unsigned DwordOffset) const;
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void lowerImplicitParameter(MachineInstr *MI, MachineBasicBlock &BB,
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MachineRegisterInfo & MRI, unsigned dword_offset) const;
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SDValue OptimizeSwizzle(SDValue BuildVector, SDValue Swz[], SelectionDAG &DAG,
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const SDLoc &DL) const;
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SDValue vectorToVerticalVector(SelectionDAG &DAG, SDValue Vector) const;
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SDValue lowerFrameIndex(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
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SelectionDAG &DAG) const override;
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SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerPrivateTruncStore(StoreSDNode *Store, SelectionDAG &DAG) const;
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SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerPrivateExtLoad(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSHLParts(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSRXParts(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerUADDSUBO(SDValue Op, SelectionDAG &DAG,
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unsigned mainop, unsigned ovf) const;
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SDValue stackPtrToRegIndex(SDValue Ptr, unsigned StackWidth,
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SelectionDAG &DAG) const;
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void getStackAddress(unsigned StackWidth, unsigned ElemIdx,
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unsigned &Channel, unsigned &PtrIncr) const;
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bool isZero(SDValue Op) const;
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bool isHWTrueValue(SDValue Op) const;
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bool isHWFalseValue(SDValue Op) const;
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bool FoldOperand(SDNode *ParentNode, unsigned SrcIdx, SDValue &Src,
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SDValue &Neg, SDValue &Abs, SDValue &Sel, SDValue &Imm,
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SelectionDAG &DAG) const;
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SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override;
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};
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} // End namespace llvm;
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#endif
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