llvm-project/llvm/test
Matt Arsenault 4b4496312e AMDGPU: Start adding MODE register uses to instructions
This is the groundwork required to implement strictfp. For now, this
should be NFC for regular instructoins (many instructions just gain an
extra use of a reserved register). Regalloc won't rematerialize
instructions with reads of physical registers, but we were suffering
from that anyway with the exec reads.

Should add it for all the related FP uses (possibly with some
extras). I did not add it to either the gpr index mode instructions
(or every single VALU instruction) since it's a ridiculous feature
already modeled as an arbitrary side effect.

Also work towards marking instructions with FP exceptions. This
doesn't actually set the bit yet since this would start to change
codegen. It seems nofpexcept is currently not implied from the regular
IR FP operations. Add it to some MIR tests where I think it might
matter.
2020-05-27 14:47:00 -04:00
..
Analysis [StackSafety] Bailout on some function calls 2020-05-27 02:48:42 -07:00
Assembler AllocaInst should store Align instead of MaybeAlign. 2020-05-16 14:53:16 -07:00
Bindings
Bitcode StoreInst should store Align, not MaybeAlign 2020-05-15 12:26:58 -07:00
BugPoint
CodeGen AMDGPU: Start adding MODE register uses to instructions 2020-05-27 14:47:00 -04:00
DebugInfo [debuginfo] Fix broken tests from MachineLICM salvaging fix 2020-05-26 22:46:07 +01:00
Demangle Give microsoftDemangle() an outparam for how many input bytes were consumed. 2020-05-20 16:17:31 -04:00
Examples
ExecutionEngine [FPEnv] Intrinsic llvm.roundeven 2020-05-26 19:24:58 +07:00
Feature StoreInst should store Align, not MaybeAlign 2020-05-15 12:26:58 -07:00
FileCheck [FileCheck] Allow parenthesized expressions 2020-05-27 16:31:39 +01:00
Instrumentation StoreInst should store Align, not MaybeAlign 2020-05-15 12:26:58 -07:00
Integer
JitListener
LTO Infer alignment of unmarked loads in IR/bitcode parsing. 2020-05-14 13:03:50 -07:00
Linker
MC [X86] Assemble movzb 1280(%rbx, %r12), %r12 after D80608 2020-05-27 09:55:55 -07:00
MachineVerifier GlobalISel: Merge G_PTR_MASK with llvm.ptrmask intrinsic 2020-05-26 11:48:13 -04:00
Object [yaml2obj] - Stop using square brackets for unique suffixes. 2020-05-19 12:59:13 +03:00
ObjectYAML
Other [Pass Manager] remove EarlyCSE as clean-up for VectorCombine 2020-05-24 12:36:21 -04:00
Reduce
SafepointIRVerifier
Support On Windows, handle interrupt signals without crash message 2020-05-21 13:27:10 +01:00
SymbolRewriter
TableGen [TableGen] Fix register class handling in TableGen's DAG ISel Matcher Generator 2020-05-13 10:17:03 +01:00
ThinLTO/X86 [LTO] Suppress emission of empty combined module by default 2020-05-04 18:31:09 -07:00
Transforms [UnJ] Update LI for inner nested loops 2020-05-27 14:36:38 +01:00
Unit
Verifier Modify verifier checks to support musttail + preallocated 2020-05-26 15:20:20 -07:00
YAMLParser
tools [llvm-readobj] - Do not crash when an invalid .eh_frame_hdr is dumped using --unwind. 2020-05-27 16:41:09 +03:00
.clang-format
CMakeLists.txt [examples] Skip building the Bye pass plugin on windows 2020-05-13 13:40:56 +03:00
TestRunner.sh
lit.cfg.py
lit.site.cfg.py.in Revert "Temporarily revert "build: use `find_package(Python3)` if available"" 2020-04-29 01:38:08 +00:00