llvm-project/llvm/test/CodeGen
Simon Pilgrim 46dd55f1e1 [X86][SSE] Change BUILD_VECTOR interleaving ordering to improve coalescing/combine opportunities
We currently generate BUILD_VECTOR as a tree of UNPCKL shuffles of the same type:

e.g. for v4f32:

Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
      : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
Step 2: unpcklps X, Y ==>    <3, 2, 1, 0>

The issue is because we are not placing sequential vector elements together early enough, we fail to recognise many combinable patterns - consecutive scalar loads, extractions etc.

Instead, this patch unpacks progressively larger sequential vector elements together:

e.g. for v4f32:

Step 1: unpcklps 0, 2 ==> X: <?, ?, 1, 0>
      : unpcklps 1, 3 ==> Y: <?, ?, 3, 2>
Step 2: unpcklpd X, Y ==>    <3, 2, 1, 0>

This does mean that we are creating UNPCKL shuffle of different value types, but the relevant combines that benefit from this are quite capable of handling the additional BITCASTs that are now included in the shuffle tree.

Differential Revision: https://reviews.llvm.org/D33864

llvm-svn: 304688
2017-06-04 20:12:04 +00:00
..
AArch64 Fix addcarry-crash.ll 2017-06-01 14:24:31 +00:00
AMDGPU [AMDGPU] Untangle SDWA pass from SIShrinkInstructions 2017-06-03 17:39:47 +00:00
ARM [GlobalMerge] Don't merge globals that may be preempted 2017-06-02 10:24:14 +00:00
AVR [AVR] Fix a big in shift operator lowering; Authored by Dr. Gergo Erdi 2017-05-31 06:27:46 +00:00
BPF [bpf] fix a bug which causes incorrect big endian reloc fixup 2017-05-05 18:05:00 +00:00
Generic [LegacyPassManager] Remove TargetMachine constructors 2017-05-18 17:21:13 +00:00
Hexagon [Hexagon] Return 0 from getDotNewPredOp when .new opcode does not exist 2017-06-02 14:07:06 +00:00
Inputs
Lanai CodeGen: Rename DEBUG_TYPE to match passnames 2017-05-25 21:26:32 +00:00
MIR [RABasic] Properly initialize the pass 2017-06-02 22:46:26 +00:00
MSP430 [MSP430] Fix PR33050: Don't use ADD16ri to lower FrameIndex. 2017-05-24 15:08:30 +00:00
Mips [mips][microMIPS] Extending size reduction pass with LBU16, LHU16, SB16 and SH16 2017-06-02 14:14:21 +00:00
NVPTX Revert r302938 "Add LiveRangeShrink pass to shrink live range within BB." 2017-05-18 18:50:05 +00:00
Nios2 [Nios2] Target registration 2017-05-29 09:48:30 +00:00
PowerPC RegisterScavenging: Add ScavengerTest pass 2017-06-02 23:01:42 +00:00
SPARC Revert r302938 "Add LiveRangeShrink pass to shrink live range within BB." 2017-05-18 18:50:05 +00:00
SystemZ [SystemZ] Simplify test case. NFC 2017-06-02 23:40:58 +00:00
Thumb Move machine-cse-physreg.mir to test/CodeGen/Thumb 2017-05-24 17:20:47 +00:00
Thumb2 MIR: remove explicit "noVRegs" property. 2017-05-30 21:28:57 +00:00
WebAssembly [wasm] Fix test after r304117. 2017-05-29 16:32:52 +00:00
WinEH
X86 [X86][SSE] Change BUILD_VECTOR interleaving ordering to improve coalescing/combine opportunities 2017-06-04 20:12:04 +00:00
XCore AsmPrinter: mark the beginning and the end of a function in verbose mode 2017-05-23 21:22:16 +00:00