forked from OSchip/llvm-project
145 lines
6.0 KiB
TableGen
145 lines
6.0 KiB
TableGen
//=- AArch64ScheduleA53.td - ARM Cortex-A53 Scheduling Definitions -*- tablegen -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the itinerary class data for the ARM Cortex A53 processors.
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//
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//===----------------------------------------------------------------------===//
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// ===---------------------------------------------------------------------===//
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// The following definitions describe the simpler per-operand machine model.
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// This works with MachineScheduler. See MCSchedModel.h for details.
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// Cortex-A53 machine model for scheduling and other instruction cost heuristics.
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def CortexA53Model : SchedMachineModel {
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let IssueWidth = 2; // 2 micro-ops are dispatched per cycle.
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let MinLatency = 1 ; // OperandCycles are interpreted as MinLatency.
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let LoadLatency = 2; // Optimistic load latency assuming bypass.
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// This is overriden by OperandCycles if the
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// Itineraries are queried instead.
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let MispredictPenalty = 9; // Based on "Cortex-A53 Software Optimisation
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// Specification - Instruction Timings"
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// v 1.0 Spreadsheet
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}
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//===----------------------------------------------------------------------===//
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// Define each kind of processor resource and number available.
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// Modeling each pipeline as a ProcResource using the default BufferSize = -1.
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// Cortex-A53 is in-order and therefore should be using BufferSize = 0. The
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// current configuration performs better with the basic latencies provided so
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// far. Will revisit BufferSize once the latency information is more accurate.
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let SchedModel = CortexA53Model in {
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def A53UnitALU : ProcResource<2>; // Int ALU
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def A53UnitMAC : ProcResource<1>; // Int MAC
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def A53UnitDiv : ProcResource<1>; // Int Division
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def A53UnitLdSt : ProcResource<1>; // Load/Store
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def A53UnitB : ProcResource<1>; // Branch
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def A53UnitFPALU : ProcResource<1>; // FP ALU
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def A53UnitFPMDS : ProcResource<1>; // FP Mult/Div/Sqrt
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//===----------------------------------------------------------------------===//
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// Subtarget-specific SchedWrite types which both map the ProcResources and
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// set the latency.
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// Issue - Every instruction must consume an A53WriteIssue. Optionally,
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// instructions that cannot be dual-issued will also include the
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// A53WriteIssue2nd in their SchedRW list. That second WriteRes will
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// ensure that a second issue slot is consumed.
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def A53WriteIssue : SchedWriteRes<[]>;
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def A53WriteIssue2nd : SchedWriteRes<[]> { let Latency = 0; }
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// ALU - These are reduced to 1 despite a true latency of 4 in order to easily
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// model forwarding logic. Once forwarding is properly modelled, then
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// they'll be corrected.
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def : WriteRes<WriteALU, [A53UnitALU]> { let Latency = 1; }
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def : WriteRes<WriteALUs, [A53UnitALU]> { let Latency = 1; }
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def : WriteRes<WriteCMP, [A53UnitALU]> { let Latency = 1; }
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// MAC
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def : WriteRes<WriteMAC, [A53UnitMAC]> { let Latency = 4; }
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// Div
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def : WriteRes<WriteDiv, [A53UnitDiv]> { let Latency = 4; }
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// Load - Note: Vector loads take 1-5 cycles to issue. For the WriteVecLd below,
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// choosing the median of 3 which makes the latency 6. May model this more
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// carefully in the future.
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def : WriteRes<WriteLd, [A53UnitLdSt]> { let Latency = 4; }
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def : WriteRes<WritePreLd, [A53UnitLdSt]> { let Latency = 4; }
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def : WriteRes<WriteVecLd, [A53UnitLdSt]> { let Latency = 6; }
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// Store - Note: Vector stores take 1-3 cycles to issue. For the ReadVecSt below,
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// choosing the median of 2 which makes the latency 5. May model this more
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// carefully in the future.
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def : WriteRes<WriteSt, [A53UnitLdSt]> { let Latency = 4; }
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def : WriteRes<WriteVecSt, [A53UnitLdSt]> { let Latency = 5; }
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// Branch
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def : WriteRes<WriteBr, [A53UnitB]>;
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def : WriteRes<WriteBrL, [A53UnitB]>;
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// FP ALU
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def : WriteRes<WriteFPALU, [A53UnitFPALU]> {let Latency = 6; }
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// FP MAC, Mul, Div, Sqrt
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// Using Double Precision numbers for now as a worst case. Additionally, not
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// modeling the exact hazard but instead treating the whole pipe as a hazard.
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// As an example VMUL, VMLA, and others are actually pipelined. VDIV and VSQRT
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// have a total latency of 33 and 32 respectively but only a hazard of 29 and
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// 28 (double-prescion example).
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def : WriteRes<WriteFPMAC, [A53UnitFPMDS]> { let Latency = 10; }
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def : WriteRes<WriteFPMul, [A53UnitFPMDS]> { let Latency = 6; }
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def : WriteRes<WriteFPDiv, [A53UnitFPMDS]> { let Latency = 33;
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let ResourceCycles = [29]; }
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def : WriteRes<WriteFPSqrt, [A53UnitFPMDS]> { let Latency = 32;
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let ResourceCycles = [28]; }
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//===----------------------------------------------------------------------===//
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// Subtarget-specific SchedRead types.
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// No forwarding defined for ReadALU yet.
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def : ReadAdvance<ReadALU, 0>;
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// No forwarding defined for ReadCMP yet.
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def : ReadAdvance<ReadCMP, 0>;
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// No forwarding defined for ReadBr yet.
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def : ReadAdvance<ReadBr, 0>;
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// No forwarding defined for ReadMAC yet.
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def : ReadAdvance<ReadMAC, 0>;
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// No forwarding defined for ReadDiv yet.
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def : ReadAdvance<ReadDiv, 0>;
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// No forwarding defined for ReadLd, ReadPreLd, ReadVecLd yet.
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def : ReadAdvance<ReadLd, 0>;
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def : ReadAdvance<ReadPreLd, 0>;
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def : ReadAdvance<ReadVecLd, 0>;
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// No forwarding defined for ReadSt and ReadVecSt yet.
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def : ReadAdvance<ReadSt, 0>;
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def : ReadAdvance<ReadVecSt, 0>;
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// No forwarding defined for ReadFPALU yet.
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def : ReadAdvance<ReadFPALU, 0>;
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// No forwarding defined for ReadFPMAC/Mul/Div/Sqrt yet.
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def : ReadAdvance<ReadFPMAC, 0>;
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def : ReadAdvance<ReadFPMul, 0>;
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def : ReadAdvance<ReadFPDiv, 0>;
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def : ReadAdvance<ReadFPSqrt, 0>;
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}
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