forked from OSchip/llvm-project
119 lines
4.5 KiB
C++
119 lines
4.5 KiB
C++
//===-- NVPTXTargetTransformInfo.h - NVPTX specific TTI ---------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file a TargetTransformInfo::Concept conforming object specific to the
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/// NVPTX target machine. It uses the target's detailed information to
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/// provide more precise answers to certain TTI queries, while letting the
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/// target independent and default TTI implementations handle the rest.
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///
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_NVPTX_NVPTXTARGETTRANSFORMINFO_H
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#define LLVM_LIB_TARGET_NVPTX_NVPTXTARGETTRANSFORMINFO_H
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#include "NVPTX.h"
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#include "NVPTXTargetMachine.h"
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#include "llvm/Analysis/TargetTransformInfo.h"
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#include "llvm/CodeGen/BasicTTIImpl.h"
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#include "llvm/CodeGen/TargetLowering.h"
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namespace llvm {
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class NVPTXTTIImpl : public BasicTTIImplBase<NVPTXTTIImpl> {
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typedef BasicTTIImplBase<NVPTXTTIImpl> BaseT;
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typedef TargetTransformInfo TTI;
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friend BaseT;
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const NVPTXSubtarget *ST;
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const NVPTXTargetLowering *TLI;
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const NVPTXSubtarget *getST() const { return ST; };
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const NVPTXTargetLowering *getTLI() const { return TLI; };
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public:
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explicit NVPTXTTIImpl(const NVPTXTargetMachine *TM, const Function &F)
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: BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl()),
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TLI(ST->getTargetLowering()) {}
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bool hasBranchDivergence() { return true; }
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bool isSourceOfDivergence(const Value *V);
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unsigned getFlatAddressSpace() const {
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return AddressSpace::ADDRESS_SPACE_GENERIC;
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}
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// Loads and stores can be vectorized if the alignment is at least as big as
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// the load/store we want to vectorize.
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bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes,
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unsigned Alignment,
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unsigned AddrSpace) const {
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return Alignment >= ChainSizeInBytes;
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}
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bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes,
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unsigned Alignment,
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unsigned AddrSpace) const {
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return isLegalToVectorizeLoadChain(ChainSizeInBytes, Alignment, AddrSpace);
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}
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// NVPTX has infinite registers of all kinds, but the actual machine doesn't.
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// We conservatively return 1 here which is just enough to enable the
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// vectorizers but disables heuristics based on the number of registers.
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// FIXME: Return a more reasonable number, while keeping an eye on
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// LoopVectorizer's unrolling heuristics.
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unsigned getNumberOfRegisters(bool Vector) const { return 1; }
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// Only <2 x half> should be vectorized, so always return 32 for the vector
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// register size.
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unsigned getRegisterBitWidth(bool Vector) const { return 32; }
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unsigned getMinVectorRegisterBitWidth() const { return 32; }
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// We don't want to prevent inlining because of target-cpu and -features
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// attributes that were added to newer versions of LLVM/Clang: There are
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// no incompatible functions in PTX, ptxas will throw errors in such cases.
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bool areInlineCompatible(const Function *Caller,
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const Function *Callee) const {
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return true;
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}
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// Increase the inlining cost threshold by a factor of 5, reflecting that
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// calls are particularly expensive in NVPTX.
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unsigned getInliningThresholdMultiplier() { return 5; }
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int getArithmeticInstrCost(
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unsigned Opcode, Type *Ty,
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TTI::OperandValueKind Opd1Info = TTI::OK_AnyValue,
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TTI::OperandValueKind Opd2Info = TTI::OK_AnyValue,
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TTI::OperandValueProperties Opd1PropInfo = TTI::OP_None,
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TTI::OperandValueProperties Opd2PropInfo = TTI::OP_None,
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ArrayRef<const Value *> Args = ArrayRef<const Value *>());
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void getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
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TTI::UnrollingPreferences &UP);
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bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) {
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// Volatile loads/stores are only supported for shared and global address
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// spaces, or for generic AS that maps to them.
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if (!(AddrSpace == llvm::ADDRESS_SPACE_GENERIC ||
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AddrSpace == llvm::ADDRESS_SPACE_GLOBAL ||
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AddrSpace == llvm::ADDRESS_SPACE_SHARED))
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return false;
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switch(I->getOpcode()){
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default:
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return false;
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case Instruction::Load:
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case Instruction::Store:
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return true;
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}
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}
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};
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} // end namespace llvm
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#endif
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