forked from OSchip/llvm-project
43b5ce492d
In certain cases it is possible that transient instructions such as %reg = IMPLICIT_DEF as a single instruction in a basic block to reach the MipsHazardSchedule pass. This patch teaches MipsHazardSchedule to properly look through such cases. Reviewers: vkalintiris, zoran.jovanovic Differential Revision: https://reviews.llvm.org/D27209 llvm-svn: 289529 |
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beqc-bnec-register-constraint.ll | ||
compact-branch-implicit-def.mir | ||
compact-branch-policy.ll | ||
compact-branches-64.ll | ||
compact-branches.ll | ||
no-beqzc-bnezc.ll |