forked from OSchip/llvm-project
1626 lines
87 KiB
C
1626 lines
87 KiB
C
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
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// REQUIRES: riscv-registered-target
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// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
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#include <riscv_vector.h>
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// CHECK-RV64-LABEL: @test_vwmul_vv_i16mf4(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
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//
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vint16mf4_t test_vwmul_vv_i16mf4(vint8mf8_t op1, vint8mf8_t op2, size_t vl) {
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return vwmul(op1, op2, vl);
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}
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// CHECK-RV64-LABEL: @test_vwmul_vx_i16mf4(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
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//
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vint16mf4_t test_vwmul_vx_i16mf4(vint8mf8_t op1, int8_t op2, size_t vl) {
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return vwmul(op1, op2, vl);
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}
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// CHECK-RV64-LABEL: @test_vwmul_vv_i16mf2(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
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//
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vint16mf2_t test_vwmul_vv_i16mf2(vint8mf4_t op1, vint8mf4_t op2, size_t vl) {
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return vwmul(op1, op2, vl);
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}
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// CHECK-RV64-LABEL: @test_vwmul_vx_i16mf2(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
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//
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vint16mf2_t test_vwmul_vx_i16mf2(vint8mf4_t op1, int8_t op2, size_t vl) {
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return vwmul(op1, op2, vl);
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}
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// CHECK-RV64-LABEL: @test_vwmul_vv_i16m1(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
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//
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vint16m1_t test_vwmul_vv_i16m1(vint8mf2_t op1, vint8mf2_t op2, size_t vl) {
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return vwmul(op1, op2, vl);
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}
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// CHECK-RV64-LABEL: @test_vwmul_vx_i16m1(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
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//
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vint16m1_t test_vwmul_vx_i16m1(vint8mf2_t op1, int8_t op2, size_t vl) {
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return vwmul(op1, op2, vl);
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}
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// CHECK-RV64-LABEL: @test_vwmul_vv_i16m2(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
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//
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vint16m2_t test_vwmul_vv_i16m2(vint8m1_t op1, vint8m1_t op2, size_t vl) {
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return vwmul(op1, op2, vl);
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}
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// CHECK-RV64-LABEL: @test_vwmul_vx_i16m2(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
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//
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vint16m2_t test_vwmul_vx_i16m2(vint8m1_t op1, int8_t op2, size_t vl) {
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return vwmul(op1, op2, vl);
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}
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// CHECK-RV64-LABEL: @test_vwmul_vv_i16m4(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwmul.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
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//
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vint16m4_t test_vwmul_vv_i16m4(vint8m2_t op1, vint8m2_t op2, size_t vl) {
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return vwmul(op1, op2, vl);
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}
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// CHECK-RV64-LABEL: @test_vwmul_vx_i16m4(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwmul.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
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//
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vint16m4_t test_vwmul_vx_i16m4(vint8m2_t op1, int8_t op2, size_t vl) {
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return vwmul(op1, op2, vl);
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}
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// CHECK-RV64-LABEL: @test_vwmul_vv_i16m8(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwmul.nxv32i16.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
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//
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vint16m8_t test_vwmul_vv_i16m8(vint8m4_t op1, vint8m4_t op2, size_t vl) {
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return vwmul(op1, op2, vl);
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}
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// CHECK-RV64-LABEL: @test_vwmul_vx_i16m8(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwmul.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
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//
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vint16m8_t test_vwmul_vx_i16m8(vint8m4_t op1, int8_t op2, size_t vl) {
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return vwmul(op1, op2, vl);
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}
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// CHECK-RV64-LABEL: @test_vwmul_vv_i32mf2(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwmul.nxv1i32.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
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//
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vint32mf2_t test_vwmul_vv_i32mf2(vint16mf4_t op1, vint16mf4_t op2, size_t vl) {
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return vwmul(op1, op2, vl);
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}
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// CHECK-RV64-LABEL: @test_vwmul_vx_i32mf2(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwmul.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
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//
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vint32mf2_t test_vwmul_vx_i32mf2(vint16mf4_t op1, int16_t op2, size_t vl) {
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return vwmul(op1, op2, vl);
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}
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// CHECK-RV64-LABEL: @test_vwmul_vv_i32m1(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwmul.nxv2i32.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
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//
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vint32m1_t test_vwmul_vv_i32m1(vint16mf2_t op1, vint16mf2_t op2, size_t vl) {
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return vwmul(op1, op2, vl);
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}
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// CHECK-RV64-LABEL: @test_vwmul_vx_i32m1(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwmul.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
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//
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vint32m1_t test_vwmul_vx_i32m1(vint16mf2_t op1, int16_t op2, size_t vl) {
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return vwmul(op1, op2, vl);
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}
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// CHECK-RV64-LABEL: @test_vwmul_vv_i32m2(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwmul.nxv4i32.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
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//
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vint32m2_t test_vwmul_vv_i32m2(vint16m1_t op1, vint16m1_t op2, size_t vl) {
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return vwmul(op1, op2, vl);
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}
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// CHECK-RV64-LABEL: @test_vwmul_vx_i32m2(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwmul.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
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//
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vint32m2_t test_vwmul_vx_i32m2(vint16m1_t op1, int16_t op2, size_t vl) {
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return vwmul(op1, op2, vl);
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}
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// CHECK-RV64-LABEL: @test_vwmul_vv_i32m4(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwmul.nxv8i32.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
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//
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vint32m4_t test_vwmul_vv_i32m4(vint16m2_t op1, vint16m2_t op2, size_t vl) {
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return vwmul(op1, op2, vl);
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}
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// CHECK-RV64-LABEL: @test_vwmul_vx_i32m4(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwmul.nxv8i32.nxv8i16.i16.i64(<vscale x 8 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
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//
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vint32m4_t test_vwmul_vx_i32m4(vint16m2_t op1, int16_t op2, size_t vl) {
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return vwmul(op1, op2, vl);
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}
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// CHECK-RV64-LABEL: @test_vwmul_vv_i32m8(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwmul.nxv16i32.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
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//
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vint32m8_t test_vwmul_vv_i32m8(vint16m4_t op1, vint16m4_t op2, size_t vl) {
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return vwmul(op1, op2, vl);
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}
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// CHECK-RV64-LABEL: @test_vwmul_vx_i32m8(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwmul.nxv16i32.nxv16i16.i16.i64(<vscale x 16 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
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//
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vint32m8_t test_vwmul_vx_i32m8(vint16m4_t op1, int16_t op2, size_t vl) {
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return vwmul(op1, op2, vl);
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}
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// CHECK-RV64-LABEL: @test_vwmul_vv_i64m1(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwmul.nxv1i64.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
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//
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vint64m1_t test_vwmul_vv_i64m1(vint32mf2_t op1, vint32mf2_t op2, size_t vl) {
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return vwmul(op1, op2, vl);
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}
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// CHECK-RV64-LABEL: @test_vwmul_vx_i64m1(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwmul.nxv1i64.nxv1i32.i32.i64(<vscale x 1 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
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//
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vint64m1_t test_vwmul_vx_i64m1(vint32mf2_t op1, int32_t op2, size_t vl) {
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return vwmul(op1, op2, vl);
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}
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// CHECK-RV64-LABEL: @test_vwmul_vv_i64m2(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwmul.nxv2i64.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
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//
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vint64m2_t test_vwmul_vv_i64m2(vint32m1_t op1, vint32m1_t op2, size_t vl) {
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return vwmul(op1, op2, vl);
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}
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// CHECK-RV64-LABEL: @test_vwmul_vx_i64m2(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwmul.nxv2i64.nxv2i32.i32.i64(<vscale x 2 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
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//
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vint64m2_t test_vwmul_vx_i64m2(vint32m1_t op1, int32_t op2, size_t vl) {
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return vwmul(op1, op2, vl);
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}
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// CHECK-RV64-LABEL: @test_vwmul_vv_i64m4(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwmul.nxv4i64.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
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//
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vint64m4_t test_vwmul_vv_i64m4(vint32m2_t op1, vint32m2_t op2, size_t vl) {
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return vwmul(op1, op2, vl);
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}
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// CHECK-RV64-LABEL: @test_vwmul_vx_i64m4(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwmul.nxv4i64.nxv4i32.i32.i64(<vscale x 4 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
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//
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vint64m4_t test_vwmul_vx_i64m4(vint32m2_t op1, int32_t op2, size_t vl) {
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return vwmul(op1, op2, vl);
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}
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// CHECK-RV64-LABEL: @test_vwmul_vv_i64m8(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwmul.nxv8i64.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
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//
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vint64m8_t test_vwmul_vv_i64m8(vint32m4_t op1, vint32m4_t op2, size_t vl) {
|
|
return vwmul(op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmul_vx_i64m8(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwmul.nxv8i64.nxv8i32.i32.i64(<vscale x 8 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
|
|
//
|
|
vint64m8_t test_vwmul_vx_i64m8(vint32m4_t op1, int32_t op2, size_t vl) {
|
|
return vwmul(op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulu_vv_u16mf4(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
|
|
//
|
|
vuint16mf4_t test_vwmulu_vv_u16mf4(vuint8mf8_t op1, vuint8mf8_t op2, size_t vl) {
|
|
return vwmulu(op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulu_vx_u16mf4(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwmulu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
|
|
//
|
|
vuint16mf4_t test_vwmulu_vx_u16mf4(vuint8mf8_t op1, uint8_t op2, size_t vl) {
|
|
return vwmulu(op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulu_vv_u16mf2(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
|
|
//
|
|
vuint16mf2_t test_vwmulu_vv_u16mf2(vuint8mf4_t op1, vuint8mf4_t op2, size_t vl) {
|
|
return vwmulu(op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulu_vx_u16mf2(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwmulu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
|
|
//
|
|
vuint16mf2_t test_vwmulu_vx_u16mf2(vuint8mf4_t op1, uint8_t op2, size_t vl) {
|
|
return vwmulu(op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulu_vv_u16m1(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
|
|
//
|
|
vuint16m1_t test_vwmulu_vv_u16m1(vuint8mf2_t op1, vuint8mf2_t op2, size_t vl) {
|
|
return vwmulu(op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulu_vx_u16m1(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwmulu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
|
|
//
|
|
vuint16m1_t test_vwmulu_vx_u16m1(vuint8mf2_t op1, uint8_t op2, size_t vl) {
|
|
return vwmulu(op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulu_vv_u16m2(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
|
|
//
|
|
vuint16m2_t test_vwmulu_vv_u16m2(vuint8m1_t op1, vuint8m1_t op2, size_t vl) {
|
|
return vwmulu(op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulu_vx_u16m2(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwmulu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
|
|
//
|
|
vuint16m2_t test_vwmulu_vx_u16m2(vuint8m1_t op1, uint8_t op2, size_t vl) {
|
|
return vwmulu(op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulu_vv_u16m4(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwmulu.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
|
|
//
|
|
vuint16m4_t test_vwmulu_vv_u16m4(vuint8m2_t op1, vuint8m2_t op2, size_t vl) {
|
|
return vwmulu(op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulu_vx_u16m4(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwmulu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
|
|
//
|
|
vuint16m4_t test_vwmulu_vx_u16m4(vuint8m2_t op1, uint8_t op2, size_t vl) {
|
|
return vwmulu(op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulu_vv_u16m8(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwmulu.nxv32i16.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
|
|
//
|
|
vuint16m8_t test_vwmulu_vv_u16m8(vuint8m4_t op1, vuint8m4_t op2, size_t vl) {
|
|
return vwmulu(op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulu_vx_u16m8(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwmulu.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
|
|
//
|
|
vuint16m8_t test_vwmulu_vx_u16m8(vuint8m4_t op1, uint8_t op2, size_t vl) {
|
|
return vwmulu(op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulu_vv_u32mf2(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwmulu.nxv1i32.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
|
|
//
|
|
vuint32mf2_t test_vwmulu_vv_u32mf2(vuint16mf4_t op1, vuint16mf4_t op2, size_t vl) {
|
|
return vwmulu(op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulu_vx_u32mf2(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwmulu.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
|
|
//
|
|
vuint32mf2_t test_vwmulu_vx_u32mf2(vuint16mf4_t op1, uint16_t op2, size_t vl) {
|
|
return vwmulu(op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulu_vv_u32m1(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwmulu.nxv2i32.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
|
|
//
|
|
vuint32m1_t test_vwmulu_vv_u32m1(vuint16mf2_t op1, vuint16mf2_t op2, size_t vl) {
|
|
return vwmulu(op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulu_vx_u32m1(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwmulu.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
|
|
//
|
|
vuint32m1_t test_vwmulu_vx_u32m1(vuint16mf2_t op1, uint16_t op2, size_t vl) {
|
|
return vwmulu(op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulu_vv_u32m2(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwmulu.nxv4i32.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
|
|
//
|
|
vuint32m2_t test_vwmulu_vv_u32m2(vuint16m1_t op1, vuint16m1_t op2, size_t vl) {
|
|
return vwmulu(op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulu_vx_u32m2(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwmulu.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
|
|
//
|
|
vuint32m2_t test_vwmulu_vx_u32m2(vuint16m1_t op1, uint16_t op2, size_t vl) {
|
|
return vwmulu(op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulu_vv_u32m4(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwmulu.nxv8i32.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
|
|
//
|
|
vuint32m4_t test_vwmulu_vv_u32m4(vuint16m2_t op1, vuint16m2_t op2, size_t vl) {
|
|
return vwmulu(op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulu_vx_u32m4(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwmulu.nxv8i32.nxv8i16.i16.i64(<vscale x 8 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
|
|
//
|
|
vuint32m4_t test_vwmulu_vx_u32m4(vuint16m2_t op1, uint16_t op2, size_t vl) {
|
|
return vwmulu(op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulu_vv_u32m8(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwmulu.nxv16i32.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
|
|
//
|
|
vuint32m8_t test_vwmulu_vv_u32m8(vuint16m4_t op1, vuint16m4_t op2, size_t vl) {
|
|
return vwmulu(op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulu_vx_u32m8(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwmulu.nxv16i32.nxv16i16.i16.i64(<vscale x 16 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
|
|
//
|
|
vuint32m8_t test_vwmulu_vx_u32m8(vuint16m4_t op1, uint16_t op2, size_t vl) {
|
|
return vwmulu(op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulu_vv_u64m1(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwmulu.nxv1i64.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
|
|
//
|
|
vuint64m1_t test_vwmulu_vv_u64m1(vuint32mf2_t op1, vuint32mf2_t op2, size_t vl) {
|
|
return vwmulu(op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulu_vx_u64m1(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwmulu.nxv1i64.nxv1i32.i32.i64(<vscale x 1 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
|
|
//
|
|
vuint64m1_t test_vwmulu_vx_u64m1(vuint32mf2_t op1, uint32_t op2, size_t vl) {
|
|
return vwmulu(op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulu_vv_u64m2(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwmulu.nxv2i64.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
|
|
//
|
|
vuint64m2_t test_vwmulu_vv_u64m2(vuint32m1_t op1, vuint32m1_t op2, size_t vl) {
|
|
return vwmulu(op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulu_vx_u64m2(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwmulu.nxv2i64.nxv2i32.i32.i64(<vscale x 2 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
|
|
//
|
|
vuint64m2_t test_vwmulu_vx_u64m2(vuint32m1_t op1, uint32_t op2, size_t vl) {
|
|
return vwmulu(op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulu_vv_u64m4(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwmulu.nxv4i64.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
|
|
//
|
|
vuint64m4_t test_vwmulu_vv_u64m4(vuint32m2_t op1, vuint32m2_t op2, size_t vl) {
|
|
return vwmulu(op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulu_vx_u64m4(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwmulu.nxv4i64.nxv4i32.i32.i64(<vscale x 4 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
|
|
//
|
|
vuint64m4_t test_vwmulu_vx_u64m4(vuint32m2_t op1, uint32_t op2, size_t vl) {
|
|
return vwmulu(op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulu_vv_u64m8(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwmulu.nxv8i64.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
|
|
//
|
|
vuint64m8_t test_vwmulu_vv_u64m8(vuint32m4_t op1, vuint32m4_t op2, size_t vl) {
|
|
return vwmulu(op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulu_vx_u64m8(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwmulu.nxv8i64.nxv8i32.i32.i64(<vscale x 8 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
|
|
//
|
|
vuint64m8_t test_vwmulu_vx_u64m8(vuint32m4_t op1, uint32_t op2, size_t vl) {
|
|
return vwmulu(op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulsu_vv_i16mf4(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
|
|
//
|
|
vint16mf4_t test_vwmulsu_vv_i16mf4(vint8mf8_t op1, vuint8mf8_t op2, size_t vl) {
|
|
return vwmulsu(op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulsu_vx_i16mf4(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
|
|
//
|
|
vint16mf4_t test_vwmulsu_vx_i16mf4(vint8mf8_t op1, uint8_t op2, size_t vl) {
|
|
return vwmulsu(op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulsu_vv_i16mf2(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
|
|
//
|
|
vint16mf2_t test_vwmulsu_vv_i16mf2(vint8mf4_t op1, vuint8mf4_t op2, size_t vl) {
|
|
return vwmulsu(op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulsu_vx_i16mf2(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
|
|
//
|
|
vint16mf2_t test_vwmulsu_vx_i16mf2(vint8mf4_t op1, uint8_t op2, size_t vl) {
|
|
return vwmulsu(op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulsu_vv_i16m1(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
|
|
//
|
|
vint16m1_t test_vwmulsu_vv_i16m1(vint8mf2_t op1, vuint8mf2_t op2, size_t vl) {
|
|
return vwmulsu(op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulsu_vx_i16m1(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
|
|
//
|
|
vint16m1_t test_vwmulsu_vx_i16m1(vint8mf2_t op1, uint8_t op2, size_t vl) {
|
|
return vwmulsu(op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulsu_vv_i16m2(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
|
|
//
|
|
vint16m2_t test_vwmulsu_vv_i16m2(vint8m1_t op1, vuint8m1_t op2, size_t vl) {
|
|
return vwmulsu(op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulsu_vx_i16m2(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
|
|
//
|
|
vint16m2_t test_vwmulsu_vx_i16m2(vint8m1_t op1, uint8_t op2, size_t vl) {
|
|
return vwmulsu(op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulsu_vv_i16m4(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
|
|
//
|
|
vint16m4_t test_vwmulsu_vv_i16m4(vint8m2_t op1, vuint8m2_t op2, size_t vl) {
|
|
return vwmulsu(op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulsu_vx_i16m4(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
|
|
//
|
|
vint16m4_t test_vwmulsu_vx_i16m4(vint8m2_t op1, uint8_t op2, size_t vl) {
|
|
return vwmulsu(op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulsu_vv_i16m8(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwmulsu.nxv32i16.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
|
|
//
|
|
vint16m8_t test_vwmulsu_vv_i16m8(vint8m4_t op1, vuint8m4_t op2, size_t vl) {
|
|
return vwmulsu(op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulsu_vx_i16m8(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwmulsu.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
|
|
//
|
|
vint16m8_t test_vwmulsu_vx_i16m8(vint8m4_t op1, uint8_t op2, size_t vl) {
|
|
return vwmulsu(op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulsu_vv_i32mf2(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwmulsu.nxv1i32.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
|
|
//
|
|
vint32mf2_t test_vwmulsu_vv_i32mf2(vint16mf4_t op1, vuint16mf4_t op2, size_t vl) {
|
|
return vwmulsu(op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulsu_vx_i32mf2(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwmulsu.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
|
|
//
|
|
vint32mf2_t test_vwmulsu_vx_i32mf2(vint16mf4_t op1, uint16_t op2, size_t vl) {
|
|
return vwmulsu(op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulsu_vv_i32m1(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwmulsu.nxv2i32.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
|
|
//
|
|
vint32m1_t test_vwmulsu_vv_i32m1(vint16mf2_t op1, vuint16mf2_t op2, size_t vl) {
|
|
return vwmulsu(op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulsu_vx_i32m1(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwmulsu.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
|
|
//
|
|
vint32m1_t test_vwmulsu_vx_i32m1(vint16mf2_t op1, uint16_t op2, size_t vl) {
|
|
return vwmulsu(op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulsu_vv_i32m2(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwmulsu.nxv4i32.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
|
|
//
|
|
vint32m2_t test_vwmulsu_vv_i32m2(vint16m1_t op1, vuint16m1_t op2, size_t vl) {
|
|
return vwmulsu(op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulsu_vx_i32m2(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwmulsu.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
|
|
//
|
|
vint32m2_t test_vwmulsu_vx_i32m2(vint16m1_t op1, uint16_t op2, size_t vl) {
|
|
return vwmulsu(op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulsu_vv_i32m4(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwmulsu.nxv8i32.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
|
|
//
|
|
vint32m4_t test_vwmulsu_vv_i32m4(vint16m2_t op1, vuint16m2_t op2, size_t vl) {
|
|
return vwmulsu(op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulsu_vx_i32m4(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwmulsu.nxv8i32.nxv8i16.i16.i64(<vscale x 8 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
|
|
//
|
|
vint32m4_t test_vwmulsu_vx_i32m4(vint16m2_t op1, uint16_t op2, size_t vl) {
|
|
return vwmulsu(op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulsu_vv_i32m8(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwmulsu.nxv16i32.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
|
|
//
|
|
vint32m8_t test_vwmulsu_vv_i32m8(vint16m4_t op1, vuint16m4_t op2, size_t vl) {
|
|
return vwmulsu(op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulsu_vx_i32m8(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwmulsu.nxv16i32.nxv16i16.i16.i64(<vscale x 16 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
|
|
//
|
|
vint32m8_t test_vwmulsu_vx_i32m8(vint16m4_t op1, uint16_t op2, size_t vl) {
|
|
return vwmulsu(op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulsu_vv_i64m1(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwmulsu.nxv1i64.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
|
|
//
|
|
vint64m1_t test_vwmulsu_vv_i64m1(vint32mf2_t op1, vuint32mf2_t op2, size_t vl) {
|
|
return vwmulsu(op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulsu_vx_i64m1(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwmulsu.nxv1i64.nxv1i32.i32.i64(<vscale x 1 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
|
|
//
|
|
vint64m1_t test_vwmulsu_vx_i64m1(vint32mf2_t op1, uint32_t op2, size_t vl) {
|
|
return vwmulsu(op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulsu_vv_i64m2(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwmulsu.nxv2i64.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
|
|
//
|
|
vint64m2_t test_vwmulsu_vv_i64m2(vint32m1_t op1, vuint32m1_t op2, size_t vl) {
|
|
return vwmulsu(op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulsu_vx_i64m2(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwmulsu.nxv2i64.nxv2i32.i32.i64(<vscale x 2 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
|
|
//
|
|
vint64m2_t test_vwmulsu_vx_i64m2(vint32m1_t op1, uint32_t op2, size_t vl) {
|
|
return vwmulsu(op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulsu_vv_i64m4(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwmulsu.nxv4i64.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
|
|
//
|
|
vint64m4_t test_vwmulsu_vv_i64m4(vint32m2_t op1, vuint32m2_t op2, size_t vl) {
|
|
return vwmulsu(op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulsu_vx_i64m4(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwmulsu.nxv4i64.nxv4i32.i32.i64(<vscale x 4 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
|
|
//
|
|
vint64m4_t test_vwmulsu_vx_i64m4(vint32m2_t op1, uint32_t op2, size_t vl) {
|
|
return vwmulsu(op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulsu_vv_i64m8(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwmulsu.nxv8i64.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
|
|
//
|
|
vint64m8_t test_vwmulsu_vv_i64m8(vint32m4_t op1, vuint32m4_t op2, size_t vl) {
|
|
return vwmulsu(op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulsu_vx_i64m8(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwmulsu.nxv8i64.nxv8i32.i32.i64(<vscale x 8 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
|
|
//
|
|
vint64m8_t test_vwmulsu_vx_i64m8(vint32m4_t op1, uint32_t op2, size_t vl) {
|
|
return vwmulsu(op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmul_vv_i16mf4_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwmul.mask.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
|
|
//
|
|
vint16mf4_t test_vwmul_vv_i16mf4_m(vbool64_t mask, vint16mf4_t maskedoff, vint8mf8_t op1, vint8mf8_t op2, size_t vl) {
|
|
return vwmul(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmul_vx_i16mf4_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwmul.mask.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
|
|
//
|
|
vint16mf4_t test_vwmul_vx_i16mf4_m(vbool64_t mask, vint16mf4_t maskedoff, vint8mf8_t op1, int8_t op2, size_t vl) {
|
|
return vwmul(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmul_vv_i16mf2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwmul.mask.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
|
|
//
|
|
vint16mf2_t test_vwmul_vv_i16mf2_m(vbool32_t mask, vint16mf2_t maskedoff, vint8mf4_t op1, vint8mf4_t op2, size_t vl) {
|
|
return vwmul(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmul_vx_i16mf2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwmul.mask.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
|
|
//
|
|
vint16mf2_t test_vwmul_vx_i16mf2_m(vbool32_t mask, vint16mf2_t maskedoff, vint8mf4_t op1, int8_t op2, size_t vl) {
|
|
return vwmul(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmul_vv_i16m1_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwmul.mask.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
|
|
//
|
|
vint16m1_t test_vwmul_vv_i16m1_m(vbool16_t mask, vint16m1_t maskedoff, vint8mf2_t op1, vint8mf2_t op2, size_t vl) {
|
|
return vwmul(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmul_vx_i16m1_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwmul.mask.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
|
|
//
|
|
vint16m1_t test_vwmul_vx_i16m1_m(vbool16_t mask, vint16m1_t maskedoff, vint8mf2_t op1, int8_t op2, size_t vl) {
|
|
return vwmul(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmul_vv_i16m2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwmul.mask.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
|
|
//
|
|
vint16m2_t test_vwmul_vv_i16m2_m(vbool8_t mask, vint16m2_t maskedoff, vint8m1_t op1, vint8m1_t op2, size_t vl) {
|
|
return vwmul(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmul_vx_i16m2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwmul.mask.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
|
|
//
|
|
vint16m2_t test_vwmul_vx_i16m2_m(vbool8_t mask, vint16m2_t maskedoff, vint8m1_t op1, int8_t op2, size_t vl) {
|
|
return vwmul(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmul_vv_i16m4_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwmul.mask.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
|
|
//
|
|
vint16m4_t test_vwmul_vv_i16m4_m(vbool4_t mask, vint16m4_t maskedoff, vint8m2_t op1, vint8m2_t op2, size_t vl) {
|
|
return vwmul(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmul_vx_i16m4_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwmul.mask.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
|
|
//
|
|
vint16m4_t test_vwmul_vx_i16m4_m(vbool4_t mask, vint16m4_t maskedoff, vint8m2_t op1, int8_t op2, size_t vl) {
|
|
return vwmul(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmul_vv_i16m8_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwmul.mask.nxv32i16.nxv32i8.nxv32i8.i64(<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
|
|
//
|
|
vint16m8_t test_vwmul_vv_i16m8_m(vbool2_t mask, vint16m8_t maskedoff, vint8m4_t op1, vint8m4_t op2, size_t vl) {
|
|
return vwmul(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmul_vx_i16m8_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwmul.mask.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
|
|
//
|
|
vint16m8_t test_vwmul_vx_i16m8_m(vbool2_t mask, vint16m8_t maskedoff, vint8m4_t op1, int8_t op2, size_t vl) {
|
|
return vwmul(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmul_vv_i32mf2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwmul.mask.nxv1i32.nxv1i16.nxv1i16.i64(<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
|
|
//
|
|
vint32mf2_t test_vwmul_vv_i32mf2_m(vbool64_t mask, vint32mf2_t maskedoff, vint16mf4_t op1, vint16mf4_t op2, size_t vl) {
|
|
return vwmul(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmul_vx_i32mf2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwmul.mask.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
|
|
//
|
|
vint32mf2_t test_vwmul_vx_i32mf2_m(vbool64_t mask, vint32mf2_t maskedoff, vint16mf4_t op1, int16_t op2, size_t vl) {
|
|
return vwmul(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmul_vv_i32m1_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwmul.mask.nxv2i32.nxv2i16.nxv2i16.i64(<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
|
|
//
|
|
vint32m1_t test_vwmul_vv_i32m1_m(vbool32_t mask, vint32m1_t maskedoff, vint16mf2_t op1, vint16mf2_t op2, size_t vl) {
|
|
return vwmul(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmul_vx_i32m1_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwmul.mask.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
|
|
//
|
|
vint32m1_t test_vwmul_vx_i32m1_m(vbool32_t mask, vint32m1_t maskedoff, vint16mf2_t op1, int16_t op2, size_t vl) {
|
|
return vwmul(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmul_vv_i32m2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwmul.mask.nxv4i32.nxv4i16.nxv4i16.i64(<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
|
|
//
|
|
vint32m2_t test_vwmul_vv_i32m2_m(vbool16_t mask, vint32m2_t maskedoff, vint16m1_t op1, vint16m1_t op2, size_t vl) {
|
|
return vwmul(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmul_vx_i32m2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwmul.mask.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
|
|
//
|
|
vint32m2_t test_vwmul_vx_i32m2_m(vbool16_t mask, vint32m2_t maskedoff, vint16m1_t op1, int16_t op2, size_t vl) {
|
|
return vwmul(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmul_vv_i32m4_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwmul.mask.nxv8i32.nxv8i16.nxv8i16.i64(<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
|
|
//
|
|
vint32m4_t test_vwmul_vv_i32m4_m(vbool8_t mask, vint32m4_t maskedoff, vint16m2_t op1, vint16m2_t op2, size_t vl) {
|
|
return vwmul(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmul_vx_i32m4_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwmul.mask.nxv8i32.nxv8i16.i16.i64(<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
|
|
//
|
|
vint32m4_t test_vwmul_vx_i32m4_m(vbool8_t mask, vint32m4_t maskedoff, vint16m2_t op1, int16_t op2, size_t vl) {
|
|
return vwmul(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmul_vv_i32m8_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwmul.mask.nxv16i32.nxv16i16.nxv16i16.i64(<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
|
|
//
|
|
vint32m8_t test_vwmul_vv_i32m8_m(vbool4_t mask, vint32m8_t maskedoff, vint16m4_t op1, vint16m4_t op2, size_t vl) {
|
|
return vwmul(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmul_vx_i32m8_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwmul.mask.nxv16i32.nxv16i16.i16.i64(<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
|
|
//
|
|
vint32m8_t test_vwmul_vx_i32m8_m(vbool4_t mask, vint32m8_t maskedoff, vint16m4_t op1, int16_t op2, size_t vl) {
|
|
return vwmul(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmul_vv_i64m1_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwmul.mask.nxv1i64.nxv1i32.nxv1i32.i64(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
|
|
//
|
|
vint64m1_t test_vwmul_vv_i64m1_m(vbool64_t mask, vint64m1_t maskedoff, vint32mf2_t op1, vint32mf2_t op2, size_t vl) {
|
|
return vwmul(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmul_vx_i64m1_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwmul.mask.nxv1i64.nxv1i32.i32.i64(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
|
|
//
|
|
vint64m1_t test_vwmul_vx_i64m1_m(vbool64_t mask, vint64m1_t maskedoff, vint32mf2_t op1, int32_t op2, size_t vl) {
|
|
return vwmul(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmul_vv_i64m2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwmul.mask.nxv2i64.nxv2i32.nxv2i32.i64(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
|
|
//
|
|
vint64m2_t test_vwmul_vv_i64m2_m(vbool32_t mask, vint64m2_t maskedoff, vint32m1_t op1, vint32m1_t op2, size_t vl) {
|
|
return vwmul(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmul_vx_i64m2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwmul.mask.nxv2i64.nxv2i32.i32.i64(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
|
|
//
|
|
vint64m2_t test_vwmul_vx_i64m2_m(vbool32_t mask, vint64m2_t maskedoff, vint32m1_t op1, int32_t op2, size_t vl) {
|
|
return vwmul(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmul_vv_i64m4_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwmul.mask.nxv4i64.nxv4i32.nxv4i32.i64(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
|
|
//
|
|
vint64m4_t test_vwmul_vv_i64m4_m(vbool16_t mask, vint64m4_t maskedoff, vint32m2_t op1, vint32m2_t op2, size_t vl) {
|
|
return vwmul(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmul_vx_i64m4_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwmul.mask.nxv4i64.nxv4i32.i32.i64(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
|
|
//
|
|
vint64m4_t test_vwmul_vx_i64m4_m(vbool16_t mask, vint64m4_t maskedoff, vint32m2_t op1, int32_t op2, size_t vl) {
|
|
return vwmul(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmul_vv_i64m8_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwmul.mask.nxv8i64.nxv8i32.nxv8i32.i64(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
|
|
//
|
|
vint64m8_t test_vwmul_vv_i64m8_m(vbool8_t mask, vint64m8_t maskedoff, vint32m4_t op1, vint32m4_t op2, size_t vl) {
|
|
return vwmul(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmul_vx_i64m8_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwmul.mask.nxv8i64.nxv8i32.i32.i64(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
|
|
//
|
|
vint64m8_t test_vwmul_vx_i64m8_m(vbool8_t mask, vint64m8_t maskedoff, vint32m4_t op1, int32_t op2, size_t vl) {
|
|
return vwmul(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulu_vv_u16mf4_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwmulu.mask.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
|
|
//
|
|
vuint16mf4_t test_vwmulu_vv_u16mf4_m(vbool64_t mask, vuint16mf4_t maskedoff, vuint8mf8_t op1, vuint8mf8_t op2, size_t vl) {
|
|
return vwmulu(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulu_vx_u16mf4_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwmulu.mask.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
|
|
//
|
|
vuint16mf4_t test_vwmulu_vx_u16mf4_m(vbool64_t mask, vuint16mf4_t maskedoff, vuint8mf8_t op1, uint8_t op2, size_t vl) {
|
|
return vwmulu(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulu_vv_u16mf2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwmulu.mask.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
|
|
//
|
|
vuint16mf2_t test_vwmulu_vv_u16mf2_m(vbool32_t mask, vuint16mf2_t maskedoff, vuint8mf4_t op1, vuint8mf4_t op2, size_t vl) {
|
|
return vwmulu(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulu_vx_u16mf2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwmulu.mask.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
|
|
//
|
|
vuint16mf2_t test_vwmulu_vx_u16mf2_m(vbool32_t mask, vuint16mf2_t maskedoff, vuint8mf4_t op1, uint8_t op2, size_t vl) {
|
|
return vwmulu(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulu_vv_u16m1_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwmulu.mask.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
|
|
//
|
|
vuint16m1_t test_vwmulu_vv_u16m1_m(vbool16_t mask, vuint16m1_t maskedoff, vuint8mf2_t op1, vuint8mf2_t op2, size_t vl) {
|
|
return vwmulu(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulu_vx_u16m1_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwmulu.mask.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
|
|
//
|
|
vuint16m1_t test_vwmulu_vx_u16m1_m(vbool16_t mask, vuint16m1_t maskedoff, vuint8mf2_t op1, uint8_t op2, size_t vl) {
|
|
return vwmulu(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulu_vv_u16m2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwmulu.mask.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
|
|
//
|
|
vuint16m2_t test_vwmulu_vv_u16m2_m(vbool8_t mask, vuint16m2_t maskedoff, vuint8m1_t op1, vuint8m1_t op2, size_t vl) {
|
|
return vwmulu(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulu_vx_u16m2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwmulu.mask.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
|
|
//
|
|
vuint16m2_t test_vwmulu_vx_u16m2_m(vbool8_t mask, vuint16m2_t maskedoff, vuint8m1_t op1, uint8_t op2, size_t vl) {
|
|
return vwmulu(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulu_vv_u16m4_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwmulu.mask.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
|
|
//
|
|
vuint16m4_t test_vwmulu_vv_u16m4_m(vbool4_t mask, vuint16m4_t maskedoff, vuint8m2_t op1, vuint8m2_t op2, size_t vl) {
|
|
return vwmulu(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulu_vx_u16m4_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwmulu.mask.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
|
|
//
|
|
vuint16m4_t test_vwmulu_vx_u16m4_m(vbool4_t mask, vuint16m4_t maskedoff, vuint8m2_t op1, uint8_t op2, size_t vl) {
|
|
return vwmulu(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulu_vv_u16m8_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwmulu.mask.nxv32i16.nxv32i8.nxv32i8.i64(<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
|
|
//
|
|
vuint16m8_t test_vwmulu_vv_u16m8_m(vbool2_t mask, vuint16m8_t maskedoff, vuint8m4_t op1, vuint8m4_t op2, size_t vl) {
|
|
return vwmulu(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulu_vx_u16m8_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwmulu.mask.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
|
|
//
|
|
vuint16m8_t test_vwmulu_vx_u16m8_m(vbool2_t mask, vuint16m8_t maskedoff, vuint8m4_t op1, uint8_t op2, size_t vl) {
|
|
return vwmulu(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulu_vv_u32mf2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwmulu.mask.nxv1i32.nxv1i16.nxv1i16.i64(<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
|
|
//
|
|
vuint32mf2_t test_vwmulu_vv_u32mf2_m(vbool64_t mask, vuint32mf2_t maskedoff, vuint16mf4_t op1, vuint16mf4_t op2, size_t vl) {
|
|
return vwmulu(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulu_vx_u32mf2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwmulu.mask.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
|
|
//
|
|
vuint32mf2_t test_vwmulu_vx_u32mf2_m(vbool64_t mask, vuint32mf2_t maskedoff, vuint16mf4_t op1, uint16_t op2, size_t vl) {
|
|
return vwmulu(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulu_vv_u32m1_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwmulu.mask.nxv2i32.nxv2i16.nxv2i16.i64(<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
|
|
//
|
|
vuint32m1_t test_vwmulu_vv_u32m1_m(vbool32_t mask, vuint32m1_t maskedoff, vuint16mf2_t op1, vuint16mf2_t op2, size_t vl) {
|
|
return vwmulu(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulu_vx_u32m1_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwmulu.mask.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
|
|
//
|
|
vuint32m1_t test_vwmulu_vx_u32m1_m(vbool32_t mask, vuint32m1_t maskedoff, vuint16mf2_t op1, uint16_t op2, size_t vl) {
|
|
return vwmulu(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulu_vv_u32m2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwmulu.mask.nxv4i32.nxv4i16.nxv4i16.i64(<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
|
|
//
|
|
vuint32m2_t test_vwmulu_vv_u32m2_m(vbool16_t mask, vuint32m2_t maskedoff, vuint16m1_t op1, vuint16m1_t op2, size_t vl) {
|
|
return vwmulu(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulu_vx_u32m2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwmulu.mask.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
|
|
//
|
|
vuint32m2_t test_vwmulu_vx_u32m2_m(vbool16_t mask, vuint32m2_t maskedoff, vuint16m1_t op1, uint16_t op2, size_t vl) {
|
|
return vwmulu(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulu_vv_u32m4_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwmulu.mask.nxv8i32.nxv8i16.nxv8i16.i64(<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
|
|
//
|
|
vuint32m4_t test_vwmulu_vv_u32m4_m(vbool8_t mask, vuint32m4_t maskedoff, vuint16m2_t op1, vuint16m2_t op2, size_t vl) {
|
|
return vwmulu(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulu_vx_u32m4_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwmulu.mask.nxv8i32.nxv8i16.i16.i64(<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
|
|
//
|
|
vuint32m4_t test_vwmulu_vx_u32m4_m(vbool8_t mask, vuint32m4_t maskedoff, vuint16m2_t op1, uint16_t op2, size_t vl) {
|
|
return vwmulu(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulu_vv_u32m8_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwmulu.mask.nxv16i32.nxv16i16.nxv16i16.i64(<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
|
|
//
|
|
vuint32m8_t test_vwmulu_vv_u32m8_m(vbool4_t mask, vuint32m8_t maskedoff, vuint16m4_t op1, vuint16m4_t op2, size_t vl) {
|
|
return vwmulu(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulu_vx_u32m8_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwmulu.mask.nxv16i32.nxv16i16.i16.i64(<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
|
|
//
|
|
vuint32m8_t test_vwmulu_vx_u32m8_m(vbool4_t mask, vuint32m8_t maskedoff, vuint16m4_t op1, uint16_t op2, size_t vl) {
|
|
return vwmulu(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulu_vv_u64m1_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwmulu.mask.nxv1i64.nxv1i32.nxv1i32.i64(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
|
|
//
|
|
vuint64m1_t test_vwmulu_vv_u64m1_m(vbool64_t mask, vuint64m1_t maskedoff, vuint32mf2_t op1, vuint32mf2_t op2, size_t vl) {
|
|
return vwmulu(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulu_vx_u64m1_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwmulu.mask.nxv1i64.nxv1i32.i32.i64(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
|
|
//
|
|
vuint64m1_t test_vwmulu_vx_u64m1_m(vbool64_t mask, vuint64m1_t maskedoff, vuint32mf2_t op1, uint32_t op2, size_t vl) {
|
|
return vwmulu(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulu_vv_u64m2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwmulu.mask.nxv2i64.nxv2i32.nxv2i32.i64(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
|
|
//
|
|
vuint64m2_t test_vwmulu_vv_u64m2_m(vbool32_t mask, vuint64m2_t maskedoff, vuint32m1_t op1, vuint32m1_t op2, size_t vl) {
|
|
return vwmulu(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulu_vx_u64m2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwmulu.mask.nxv2i64.nxv2i32.i32.i64(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
|
|
//
|
|
vuint64m2_t test_vwmulu_vx_u64m2_m(vbool32_t mask, vuint64m2_t maskedoff, vuint32m1_t op1, uint32_t op2, size_t vl) {
|
|
return vwmulu(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulu_vv_u64m4_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwmulu.mask.nxv4i64.nxv4i32.nxv4i32.i64(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
|
|
//
|
|
vuint64m4_t test_vwmulu_vv_u64m4_m(vbool16_t mask, vuint64m4_t maskedoff, vuint32m2_t op1, vuint32m2_t op2, size_t vl) {
|
|
return vwmulu(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulu_vx_u64m4_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwmulu.mask.nxv4i64.nxv4i32.i32.i64(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
|
|
//
|
|
vuint64m4_t test_vwmulu_vx_u64m4_m(vbool16_t mask, vuint64m4_t maskedoff, vuint32m2_t op1, uint32_t op2, size_t vl) {
|
|
return vwmulu(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulu_vv_u64m8_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwmulu.mask.nxv8i64.nxv8i32.nxv8i32.i64(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
|
|
//
|
|
vuint64m8_t test_vwmulu_vv_u64m8_m(vbool8_t mask, vuint64m8_t maskedoff, vuint32m4_t op1, vuint32m4_t op2, size_t vl) {
|
|
return vwmulu(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulu_vx_u64m8_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwmulu.mask.nxv8i64.nxv8i32.i32.i64(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
|
|
//
|
|
vuint64m8_t test_vwmulu_vx_u64m8_m(vbool8_t mask, vuint64m8_t maskedoff, vuint32m4_t op1, uint32_t op2, size_t vl) {
|
|
return vwmulu(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulsu_vv_i16mf4_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwmulsu.mask.nxv1i16.nxv1i8.nxv1i8.i64(<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], <vscale x 1 x i8> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
|
|
//
|
|
vint16mf4_t test_vwmulsu_vv_i16mf4_m(vbool64_t mask, vint16mf4_t maskedoff, vint8mf8_t op1, vuint8mf8_t op2, size_t vl) {
|
|
return vwmulsu(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulsu_vx_i16mf4_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vwmulsu.mask.nxv1i16.nxv1i8.i8.i64(<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP0]]
|
|
//
|
|
vint16mf4_t test_vwmulsu_vx_i16mf4_m(vbool64_t mask, vint16mf4_t maskedoff, vint8mf8_t op1, uint8_t op2, size_t vl) {
|
|
return vwmulsu(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulsu_vv_i16mf2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwmulsu.mask.nxv2i16.nxv2i8.nxv2i8.i64(<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], <vscale x 2 x i8> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
|
|
//
|
|
vint16mf2_t test_vwmulsu_vv_i16mf2_m(vbool32_t mask, vint16mf2_t maskedoff, vint8mf4_t op1, vuint8mf4_t op2, size_t vl) {
|
|
return vwmulsu(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulsu_vx_i16mf2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vwmulsu.mask.nxv2i16.nxv2i8.i8.i64(<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP0]]
|
|
//
|
|
vint16mf2_t test_vwmulsu_vx_i16mf2_m(vbool32_t mask, vint16mf2_t maskedoff, vint8mf4_t op1, uint8_t op2, size_t vl) {
|
|
return vwmulsu(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulsu_vv_i16m1_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwmulsu.mask.nxv4i16.nxv4i8.nxv4i8.i64(<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], <vscale x 4 x i8> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
|
|
//
|
|
vint16m1_t test_vwmulsu_vv_i16m1_m(vbool16_t mask, vint16m1_t maskedoff, vint8mf2_t op1, vuint8mf2_t op2, size_t vl) {
|
|
return vwmulsu(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulsu_vx_i16m1_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vwmulsu.mask.nxv4i16.nxv4i8.i8.i64(<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP0]]
|
|
//
|
|
vint16m1_t test_vwmulsu_vx_i16m1_m(vbool16_t mask, vint16m1_t maskedoff, vint8mf2_t op1, uint8_t op2, size_t vl) {
|
|
return vwmulsu(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulsu_vv_i16m2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwmulsu.mask.nxv8i16.nxv8i8.nxv8i8.i64(<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], <vscale x 8 x i8> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
|
|
//
|
|
vint16m2_t test_vwmulsu_vv_i16m2_m(vbool8_t mask, vint16m2_t maskedoff, vint8m1_t op1, vuint8m1_t op2, size_t vl) {
|
|
return vwmulsu(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulsu_vx_i16m2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vwmulsu.mask.nxv8i16.nxv8i8.i8.i64(<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP0]]
|
|
//
|
|
vint16m2_t test_vwmulsu_vx_i16m2_m(vbool8_t mask, vint16m2_t maskedoff, vint8m1_t op1, uint8_t op2, size_t vl) {
|
|
return vwmulsu(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulsu_vv_i16m4_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwmulsu.mask.nxv16i16.nxv16i8.nxv16i8.i64(<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
|
|
//
|
|
vint16m4_t test_vwmulsu_vv_i16m4_m(vbool4_t mask, vint16m4_t maskedoff, vint8m2_t op1, vuint8m2_t op2, size_t vl) {
|
|
return vwmulsu(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulsu_vx_i16m4_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vwmulsu.mask.nxv16i16.nxv16i8.i8.i64(<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP0]]
|
|
//
|
|
vint16m4_t test_vwmulsu_vx_i16m4_m(vbool4_t mask, vint16m4_t maskedoff, vint8m2_t op1, uint8_t op2, size_t vl) {
|
|
return vwmulsu(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulsu_vv_i16m8_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwmulsu.mask.nxv32i16.nxv32i8.nxv32i8.i64(<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[OP1:%.*]], <vscale x 32 x i8> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
|
|
//
|
|
vint16m8_t test_vwmulsu_vv_i16m8_m(vbool2_t mask, vint16m8_t maskedoff, vint8m4_t op1, vuint8m4_t op2, size_t vl) {
|
|
return vwmulsu(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulsu_vx_i16m8_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vwmulsu.mask.nxv32i16.nxv32i8.i8.i64(<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i8> [[OP1:%.*]], i8 [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP0]]
|
|
//
|
|
vint16m8_t test_vwmulsu_vx_i16m8_m(vbool2_t mask, vint16m8_t maskedoff, vint8m4_t op1, uint8_t op2, size_t vl) {
|
|
return vwmulsu(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulsu_vv_i32mf2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwmulsu.mask.nxv1i32.nxv1i16.nxv1i16.i64(<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], <vscale x 1 x i16> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
|
|
//
|
|
vint32mf2_t test_vwmulsu_vv_i32mf2_m(vbool64_t mask, vint32mf2_t maskedoff, vint16mf4_t op1, vuint16mf4_t op2, size_t vl) {
|
|
return vwmulsu(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulsu_vx_i32mf2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vwmulsu.mask.nxv1i32.nxv1i16.i16.i64(<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]]
|
|
//
|
|
vint32mf2_t test_vwmulsu_vx_i32mf2_m(vbool64_t mask, vint32mf2_t maskedoff, vint16mf4_t op1, uint16_t op2, size_t vl) {
|
|
return vwmulsu(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulsu_vv_i32m1_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwmulsu.mask.nxv2i32.nxv2i16.nxv2i16.i64(<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], <vscale x 2 x i16> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
|
|
//
|
|
vint32m1_t test_vwmulsu_vv_i32m1_m(vbool32_t mask, vint32m1_t maskedoff, vint16mf2_t op1, vuint16mf2_t op2, size_t vl) {
|
|
return vwmulsu(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulsu_vx_i32m1_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vwmulsu.mask.nxv2i32.nxv2i16.i16.i64(<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
|
|
//
|
|
vint32m1_t test_vwmulsu_vx_i32m1_m(vbool32_t mask, vint32m1_t maskedoff, vint16mf2_t op1, uint16_t op2, size_t vl) {
|
|
return vwmulsu(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulsu_vv_i32m2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwmulsu.mask.nxv4i32.nxv4i16.nxv4i16.i64(<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], <vscale x 4 x i16> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
|
|
//
|
|
vint32m2_t test_vwmulsu_vv_i32m2_m(vbool16_t mask, vint32m2_t maskedoff, vint16m1_t op1, vuint16m1_t op2, size_t vl) {
|
|
return vwmulsu(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulsu_vx_i32m2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vwmulsu.mask.nxv4i32.nxv4i16.i16.i64(<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
|
|
//
|
|
vint32m2_t test_vwmulsu_vx_i32m2_m(vbool16_t mask, vint32m2_t maskedoff, vint16m1_t op1, uint16_t op2, size_t vl) {
|
|
return vwmulsu(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulsu_vv_i32m4_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwmulsu.mask.nxv8i32.nxv8i16.nxv8i16.i64(<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
|
|
//
|
|
vint32m4_t test_vwmulsu_vv_i32m4_m(vbool8_t mask, vint32m4_t maskedoff, vint16m2_t op1, vuint16m2_t op2, size_t vl) {
|
|
return vwmulsu(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulsu_vx_i32m4_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vwmulsu.mask.nxv8i32.nxv8i16.i16.i64(<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
|
|
//
|
|
vint32m4_t test_vwmulsu_vx_i32m4_m(vbool8_t mask, vint32m4_t maskedoff, vint16m2_t op1, uint16_t op2, size_t vl) {
|
|
return vwmulsu(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulsu_vv_i32m8_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwmulsu.mask.nxv16i32.nxv16i16.nxv16i16.i64(<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], <vscale x 16 x i16> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
|
|
//
|
|
vint32m8_t test_vwmulsu_vv_i32m8_m(vbool4_t mask, vint32m8_t maskedoff, vint16m4_t op1, vuint16m4_t op2, size_t vl) {
|
|
return vwmulsu(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulsu_vx_i32m8_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vwmulsu.mask.nxv16i32.nxv16i16.i16.i64(<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i16> [[OP1:%.*]], i16 [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
|
|
//
|
|
vint32m8_t test_vwmulsu_vx_i32m8_m(vbool4_t mask, vint32m8_t maskedoff, vint16m4_t op1, uint16_t op2, size_t vl) {
|
|
return vwmulsu(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulsu_vv_i64m1_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwmulsu.mask.nxv1i64.nxv1i32.nxv1i32.i64(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], <vscale x 1 x i32> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
|
|
//
|
|
vint64m1_t test_vwmulsu_vv_i64m1_m(vbool64_t mask, vint64m1_t maskedoff, vint32mf2_t op1, vuint32mf2_t op2, size_t vl) {
|
|
return vwmulsu(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulsu_vx_i64m1_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vwmulsu.mask.nxv1i64.nxv1i32.i32.i64(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
|
|
//
|
|
vint64m1_t test_vwmulsu_vx_i64m1_m(vbool64_t mask, vint64m1_t maskedoff, vint32mf2_t op1, uint32_t op2, size_t vl) {
|
|
return vwmulsu(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulsu_vv_i64m2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwmulsu.mask.nxv2i64.nxv2i32.nxv2i32.i64(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
|
|
//
|
|
vint64m2_t test_vwmulsu_vv_i64m2_m(vbool32_t mask, vint64m2_t maskedoff, vint32m1_t op1, vuint32m1_t op2, size_t vl) {
|
|
return vwmulsu(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulsu_vx_i64m2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vwmulsu.mask.nxv2i64.nxv2i32.i32.i64(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP0]]
|
|
//
|
|
vint64m2_t test_vwmulsu_vx_i64m2_m(vbool32_t mask, vint64m2_t maskedoff, vint32m1_t op1, uint32_t op2, size_t vl) {
|
|
return vwmulsu(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulsu_vv_i64m4_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwmulsu.mask.nxv4i64.nxv4i32.nxv4i32.i64(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
|
|
//
|
|
vint64m4_t test_vwmulsu_vv_i64m4_m(vbool16_t mask, vint64m4_t maskedoff, vint32m2_t op1, vuint32m2_t op2, size_t vl) {
|
|
return vwmulsu(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulsu_vx_i64m4_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vwmulsu.mask.nxv4i64.nxv4i32.i32.i64(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP0]]
|
|
//
|
|
vint64m4_t test_vwmulsu_vx_i64m4_m(vbool16_t mask, vint64m4_t maskedoff, vint32m2_t op1, uint32_t op2, size_t vl) {
|
|
return vwmulsu(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulsu_vv_i64m8_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwmulsu.mask.nxv8i64.nxv8i32.nxv8i32.i64(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], <vscale x 8 x i32> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
|
|
//
|
|
vint64m8_t test_vwmulsu_vv_i64m8_m(vbool8_t mask, vint64m8_t maskedoff, vint32m4_t op1, vuint32m4_t op2, size_t vl) {
|
|
return vwmulsu(mask, maskedoff, op1, op2, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vwmulsu_vx_i64m8_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vwmulsu.mask.nxv8i64.nxv8i32.i32.i64(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i32> [[OP1:%.*]], i32 [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP0]]
|
|
//
|
|
vint64m8_t test_vwmulsu_vx_i64m8_m(vbool8_t mask, vint64m8_t maskedoff, vint32m4_t op1, uint32_t op2, size_t vl) {
|
|
return vwmulsu(mask, maskedoff, op1, op2, vl);
|
|
}
|