forked from OSchip/llvm-project
3827 lines
224 KiB
C
3827 lines
224 KiB
C
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
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// REQUIRES: riscv-registered-target
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// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
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// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
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#include <riscv_vector.h>
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// CHECK-RV64-LABEL: @test_vluxei8_v_i8mf8(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
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// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
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//
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vint8mf8_t test_vluxei8_v_i8mf8(const int8_t *base, vuint8mf8_t bindex, size_t vl) {
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return vluxei8(base, bindex, vl);
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}
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// CHECK-RV64-LABEL: @test_vluxei8_v_i8mf4(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
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// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]]
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//
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vint8mf4_t test_vluxei8_v_i8mf4(const int8_t *base, vuint8mf4_t bindex, size_t vl) {
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return vluxei8(base, bindex, vl);
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}
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// CHECK-RV64-LABEL: @test_vluxei8_v_i8mf2(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
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// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]]
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//
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vint8mf2_t test_vluxei8_v_i8mf2(const int8_t *base, vuint8mf2_t bindex, size_t vl) {
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return vluxei8(base, bindex, vl);
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}
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// CHECK-RV64-LABEL: @test_vluxei8_v_i8m1(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
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// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]]
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//
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vint8m1_t test_vluxei8_v_i8m1(const int8_t *base, vuint8m1_t bindex, size_t vl) {
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return vluxei8(base, bindex, vl);
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}
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// CHECK-RV64-LABEL: @test_vluxei8_v_i8m2(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
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// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vluxei.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>* [[TMP0]], <vscale x 16 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP1]]
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//
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vint8m2_t test_vluxei8_v_i8m2(const int8_t *base, vuint8m2_t bindex, size_t vl) {
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return vluxei8(base, bindex, vl);
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}
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// CHECK-RV64-LABEL: @test_vluxei8_v_i8m4(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>*
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// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vluxei.nxv32i8.nxv32i8.i64(<vscale x 32 x i8>* [[TMP0]], <vscale x 32 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP1]]
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//
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vint8m4_t test_vluxei8_v_i8m4(const int8_t *base, vuint8m4_t bindex, size_t vl) {
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return vluxei8(base, bindex, vl);
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}
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// CHECK-RV64-LABEL: @test_vluxei8_v_i8m8(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>*
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// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vluxei.nxv64i8.nxv64i8.i64(<vscale x 64 x i8>* [[TMP0]], <vscale x 64 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP1]]
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//
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vint8m8_t test_vluxei8_v_i8m8(const int8_t *base, vuint8m8_t bindex, size_t vl) {
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return vluxei8(base, bindex, vl);
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}
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// CHECK-RV64-LABEL: @test_vluxei16_v_i8mf8(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
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// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i16.i64(<vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
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//
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vint8mf8_t test_vluxei16_v_i8mf8(const int8_t *base, vuint16mf4_t bindex, size_t vl) {
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return vluxei16(base, bindex, vl);
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}
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// CHECK-RV64-LABEL: @test_vluxei16_v_i8mf4(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
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// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i16.i64(<vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]]
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//
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vint8mf4_t test_vluxei16_v_i8mf4(const int8_t *base, vuint16mf2_t bindex, size_t vl) {
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return vluxei16(base, bindex, vl);
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}
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// CHECK-RV64-LABEL: @test_vluxei16_v_i8mf2(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
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// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i16.i64(<vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]]
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//
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vint8mf2_t test_vluxei16_v_i8mf2(const int8_t *base, vuint16m1_t bindex, size_t vl) {
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return vluxei16(base, bindex, vl);
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}
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// CHECK-RV64-LABEL: @test_vluxei16_v_i8m1(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
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// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i16.i64(<vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]]
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//
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vint8m1_t test_vluxei16_v_i8m1(const int8_t *base, vuint16m2_t bindex, size_t vl) {
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return vluxei16(base, bindex, vl);
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}
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// CHECK-RV64-LABEL: @test_vluxei16_v_i8m2(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
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// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vluxei.nxv16i8.nxv16i16.i64(<vscale x 16 x i8>* [[TMP0]], <vscale x 16 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP1]]
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//
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vint8m2_t test_vluxei16_v_i8m2(const int8_t *base, vuint16m4_t bindex, size_t vl) {
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return vluxei16(base, bindex, vl);
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}
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// CHECK-RV64-LABEL: @test_vluxei16_v_i8m4(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>*
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// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vluxei.nxv32i8.nxv32i16.i64(<vscale x 32 x i8>* [[TMP0]], <vscale x 32 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP1]]
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//
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vint8m4_t test_vluxei16_v_i8m4(const int8_t *base, vuint16m8_t bindex, size_t vl) {
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return vluxei16(base, bindex, vl);
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}
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// CHECK-RV64-LABEL: @test_vluxei32_v_i8mf8(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
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// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i32.i64(<vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
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//
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vint8mf8_t test_vluxei32_v_i8mf8(const int8_t *base, vuint32mf2_t bindex, size_t vl) {
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return vluxei32(base, bindex, vl);
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}
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// CHECK-RV64-LABEL: @test_vluxei32_v_i8mf4(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
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// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i32.i64(<vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]]
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//
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vint8mf4_t test_vluxei32_v_i8mf4(const int8_t *base, vuint32m1_t bindex, size_t vl) {
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return vluxei32(base, bindex, vl);
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}
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// CHECK-RV64-LABEL: @test_vluxei32_v_i8mf2(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
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// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i32.i64(<vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]]
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//
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vint8mf2_t test_vluxei32_v_i8mf2(const int8_t *base, vuint32m2_t bindex, size_t vl) {
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return vluxei32(base, bindex, vl);
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}
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// CHECK-RV64-LABEL: @test_vluxei32_v_i8m1(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
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// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i32.i64(<vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]]
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//
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vint8m1_t test_vluxei32_v_i8m1(const int8_t *base, vuint32m4_t bindex, size_t vl) {
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return vluxei32(base, bindex, vl);
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}
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// CHECK-RV64-LABEL: @test_vluxei32_v_i8m2(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
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// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vluxei.nxv16i8.nxv16i32.i64(<vscale x 16 x i8>* [[TMP0]], <vscale x 16 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP1]]
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//
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vint8m2_t test_vluxei32_v_i8m2(const int8_t *base, vuint32m8_t bindex, size_t vl) {
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return vluxei32(base, bindex, vl);
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}
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// CHECK-RV64-LABEL: @test_vluxei64_v_i8mf8(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
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// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i64.i64(<vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
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//
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vint8mf8_t test_vluxei64_v_i8mf8(const int8_t *base, vuint64m1_t bindex, size_t vl) {
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return vluxei64(base, bindex, vl);
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}
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// CHECK-RV64-LABEL: @test_vluxei64_v_i8mf4(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
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// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i64.i64(<vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]]
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//
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vint8mf4_t test_vluxei64_v_i8mf4(const int8_t *base, vuint64m2_t bindex, size_t vl) {
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return vluxei64(base, bindex, vl);
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}
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// CHECK-RV64-LABEL: @test_vluxei64_v_i8mf2(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
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// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i64.i64(<vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]]
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//
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vint8mf2_t test_vluxei64_v_i8mf2(const int8_t *base, vuint64m4_t bindex, size_t vl) {
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return vluxei64(base, bindex, vl);
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}
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// CHECK-RV64-LABEL: @test_vluxei64_v_i8m1(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
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// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i64.i64(<vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]]
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//
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vint8m1_t test_vluxei64_v_i8m1(const int8_t *base, vuint64m8_t bindex, size_t vl) {
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return vluxei64(base, bindex, vl);
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}
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// CHECK-RV64-LABEL: @test_vluxei8_v_i16mf4(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
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// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]]
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//
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vint16mf4_t test_vluxei8_v_i16mf4(const int16_t *base, vuint8mf8_t bindex, size_t vl) {
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return vluxei8(base, bindex, vl);
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}
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// CHECK-RV64-LABEL: @test_vluxei8_v_i16mf2(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
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// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]]
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//
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vint16mf2_t test_vluxei8_v_i16mf2(const int16_t *base, vuint8mf4_t bindex, size_t vl) {
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return vluxei8(base, bindex, vl);
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}
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// CHECK-RV64-LABEL: @test_vluxei8_v_i16m1(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
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// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]]
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//
|
|
vint16m1_t test_vluxei8_v_i16m1(const int16_t *base, vuint8mf2_t bindex, size_t vl) {
|
|
return vluxei8(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_i16m2(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i8.i64(<vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]]
|
|
//
|
|
vint16m2_t test_vluxei8_v_i16m2(const int16_t *base, vuint8m1_t bindex, size_t vl) {
|
|
return vluxei8(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_i16m4(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vluxei.nxv16i16.nxv16i8.i64(<vscale x 16 x i16>* [[TMP0]], <vscale x 16 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP1]]
|
|
//
|
|
vint16m4_t test_vluxei8_v_i16m4(const int16_t *base, vuint8m2_t bindex, size_t vl) {
|
|
return vluxei8(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_i16m8(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vluxei.nxv32i16.nxv32i8.i64(<vscale x 32 x i16>* [[TMP0]], <vscale x 32 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP1]]
|
|
//
|
|
vint16m8_t test_vluxei8_v_i16m8(const int16_t *base, vuint8m4_t bindex, size_t vl) {
|
|
return vluxei8(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_i16mf4(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i16.i64(<vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]]
|
|
//
|
|
vint16mf4_t test_vluxei16_v_i16mf4(const int16_t *base, vuint16mf4_t bindex, size_t vl) {
|
|
return vluxei16(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_i16mf2(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i16.i64(<vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]]
|
|
//
|
|
vint16mf2_t test_vluxei16_v_i16mf2(const int16_t *base, vuint16mf2_t bindex, size_t vl) {
|
|
return vluxei16(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_i16m1(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i16.i64(<vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]]
|
|
//
|
|
vint16m1_t test_vluxei16_v_i16m1(const int16_t *base, vuint16m1_t bindex, size_t vl) {
|
|
return vluxei16(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_i16m2(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i16.i64(<vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]]
|
|
//
|
|
vint16m2_t test_vluxei16_v_i16m2(const int16_t *base, vuint16m2_t bindex, size_t vl) {
|
|
return vluxei16(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_i16m4(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vluxei.nxv16i16.nxv16i16.i64(<vscale x 16 x i16>* [[TMP0]], <vscale x 16 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP1]]
|
|
//
|
|
vint16m4_t test_vluxei16_v_i16m4(const int16_t *base, vuint16m4_t bindex, size_t vl) {
|
|
return vluxei16(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_i16m8(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vluxei.nxv32i16.nxv32i16.i64(<vscale x 32 x i16>* [[TMP0]], <vscale x 32 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP1]]
|
|
//
|
|
vint16m8_t test_vluxei16_v_i16m8(const int16_t *base, vuint16m8_t bindex, size_t vl) {
|
|
return vluxei16(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_i16mf4(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i32.i64(<vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]]
|
|
//
|
|
vint16mf4_t test_vluxei32_v_i16mf4(const int16_t *base, vuint32mf2_t bindex, size_t vl) {
|
|
return vluxei32(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_i16mf2(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i32.i64(<vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]]
|
|
//
|
|
vint16mf2_t test_vluxei32_v_i16mf2(const int16_t *base, vuint32m1_t bindex, size_t vl) {
|
|
return vluxei32(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_i16m1(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i32.i64(<vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]]
|
|
//
|
|
vint16m1_t test_vluxei32_v_i16m1(const int16_t *base, vuint32m2_t bindex, size_t vl) {
|
|
return vluxei32(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_i16m2(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i32.i64(<vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]]
|
|
//
|
|
vint16m2_t test_vluxei32_v_i16m2(const int16_t *base, vuint32m4_t bindex, size_t vl) {
|
|
return vluxei32(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_i16m4(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vluxei.nxv16i16.nxv16i32.i64(<vscale x 16 x i16>* [[TMP0]], <vscale x 16 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP1]]
|
|
//
|
|
vint16m4_t test_vluxei32_v_i16m4(const int16_t *base, vuint32m8_t bindex, size_t vl) {
|
|
return vluxei32(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei64_v_i16mf4(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i64.i64(<vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]]
|
|
//
|
|
vint16mf4_t test_vluxei64_v_i16mf4(const int16_t *base, vuint64m1_t bindex, size_t vl) {
|
|
return vluxei64(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei64_v_i16mf2(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i64.i64(<vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]]
|
|
//
|
|
vint16mf2_t test_vluxei64_v_i16mf2(const int16_t *base, vuint64m2_t bindex, size_t vl) {
|
|
return vluxei64(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei64_v_i16m1(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i64.i64(<vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]]
|
|
//
|
|
vint16m1_t test_vluxei64_v_i16m1(const int16_t *base, vuint64m4_t bindex, size_t vl) {
|
|
return vluxei64(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei64_v_i16m2(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i64.i64(<vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]]
|
|
//
|
|
vint16m2_t test_vluxei64_v_i16m2(const int16_t *base, vuint64m8_t bindex, size_t vl) {
|
|
return vluxei64(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_i32mf2(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i8.i64(<vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
|
|
//
|
|
vint32mf2_t test_vluxei8_v_i32mf2(const int32_t *base, vuint8mf8_t bindex, size_t vl) {
|
|
return vluxei8(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_i32m1(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i8.i64(<vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]]
|
|
//
|
|
vint32m1_t test_vluxei8_v_i32m1(const int32_t *base, vuint8mf4_t bindex, size_t vl) {
|
|
return vluxei8(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_i32m2(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i8.i64(<vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]]
|
|
//
|
|
vint32m2_t test_vluxei8_v_i32m2(const int32_t *base, vuint8mf2_t bindex, size_t vl) {
|
|
return vluxei8(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_i32m4(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i8.i64(<vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]]
|
|
//
|
|
vint32m4_t test_vluxei8_v_i32m4(const int32_t *base, vuint8m1_t bindex, size_t vl) {
|
|
return vluxei8(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_i32m8(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vluxei.nxv16i32.nxv16i8.i64(<vscale x 16 x i32>* [[TMP0]], <vscale x 16 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP1]]
|
|
//
|
|
vint32m8_t test_vluxei8_v_i32m8(const int32_t *base, vuint8m2_t bindex, size_t vl) {
|
|
return vluxei8(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_i32mf2(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i16.i64(<vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
|
|
//
|
|
vint32mf2_t test_vluxei16_v_i32mf2(const int32_t *base, vuint16mf4_t bindex, size_t vl) {
|
|
return vluxei16(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_i32m1(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i16.i64(<vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]]
|
|
//
|
|
vint32m1_t test_vluxei16_v_i32m1(const int32_t *base, vuint16mf2_t bindex, size_t vl) {
|
|
return vluxei16(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_i32m2(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i16.i64(<vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]]
|
|
//
|
|
vint32m2_t test_vluxei16_v_i32m2(const int32_t *base, vuint16m1_t bindex, size_t vl) {
|
|
return vluxei16(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_i32m4(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i16.i64(<vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]]
|
|
//
|
|
vint32m4_t test_vluxei16_v_i32m4(const int32_t *base, vuint16m2_t bindex, size_t vl) {
|
|
return vluxei16(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_i32m8(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vluxei.nxv16i32.nxv16i16.i64(<vscale x 16 x i32>* [[TMP0]], <vscale x 16 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP1]]
|
|
//
|
|
vint32m8_t test_vluxei16_v_i32m8(const int32_t *base, vuint16m4_t bindex, size_t vl) {
|
|
return vluxei16(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_i32mf2(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
|
|
//
|
|
vint32mf2_t test_vluxei32_v_i32mf2(const int32_t *base, vuint32mf2_t bindex, size_t vl) {
|
|
return vluxei32(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_i32m1(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]]
|
|
//
|
|
vint32m1_t test_vluxei32_v_i32m1(const int32_t *base, vuint32m1_t bindex, size_t vl) {
|
|
return vluxei32(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_i32m2(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]]
|
|
//
|
|
vint32m2_t test_vluxei32_v_i32m2(const int32_t *base, vuint32m2_t bindex, size_t vl) {
|
|
return vluxei32(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_i32m4(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]]
|
|
//
|
|
vint32m4_t test_vluxei32_v_i32m4(const int32_t *base, vuint32m4_t bindex, size_t vl) {
|
|
return vluxei32(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_i32m8(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vluxei.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>* [[TMP0]], <vscale x 16 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP1]]
|
|
//
|
|
vint32m8_t test_vluxei32_v_i32m8(const int32_t *base, vuint32m8_t bindex, size_t vl) {
|
|
return vluxei32(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei64_v_i32mf2(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i64.i64(<vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
|
|
//
|
|
vint32mf2_t test_vluxei64_v_i32mf2(const int32_t *base, vuint64m1_t bindex, size_t vl) {
|
|
return vluxei64(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei64_v_i32m1(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i64.i64(<vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]]
|
|
//
|
|
vint32m1_t test_vluxei64_v_i32m1(const int32_t *base, vuint64m2_t bindex, size_t vl) {
|
|
return vluxei64(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei64_v_i32m2(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i64.i64(<vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]]
|
|
//
|
|
vint32m2_t test_vluxei64_v_i32m2(const int32_t *base, vuint64m4_t bindex, size_t vl) {
|
|
return vluxei64(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei64_v_i32m4(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i64.i64(<vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]]
|
|
//
|
|
vint32m4_t test_vluxei64_v_i32m4(const int32_t *base, vuint64m8_t bindex, size_t vl) {
|
|
return vluxei64(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_i64m1(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]]
|
|
//
|
|
vint64m1_t test_vluxei8_v_i64m1(const int64_t *base, vuint8mf8_t bindex, size_t vl) {
|
|
return vluxei8(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_i64m2(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]]
|
|
//
|
|
vint64m2_t test_vluxei8_v_i64m2(const int64_t *base, vuint8mf4_t bindex, size_t vl) {
|
|
return vluxei8(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_i64m4(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]]
|
|
//
|
|
vint64m4_t test_vluxei8_v_i64m4(const int64_t *base, vuint8mf2_t bindex, size_t vl) {
|
|
return vluxei8(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_i64m8(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]]
|
|
//
|
|
vint64m8_t test_vluxei8_v_i64m8(const int64_t *base, vuint8m1_t bindex, size_t vl) {
|
|
return vluxei8(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_i64m1(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i16.i64(<vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]]
|
|
//
|
|
vint64m1_t test_vluxei16_v_i64m1(const int64_t *base, vuint16mf4_t bindex, size_t vl) {
|
|
return vluxei16(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_i64m2(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i16.i64(<vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]]
|
|
//
|
|
vint64m2_t test_vluxei16_v_i64m2(const int64_t *base, vuint16mf2_t bindex, size_t vl) {
|
|
return vluxei16(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_i64m4(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i16.i64(<vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]]
|
|
//
|
|
vint64m4_t test_vluxei16_v_i64m4(const int64_t *base, vuint16m1_t bindex, size_t vl) {
|
|
return vluxei16(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_i64m8(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i16.i64(<vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]]
|
|
//
|
|
vint64m8_t test_vluxei16_v_i64m8(const int64_t *base, vuint16m2_t bindex, size_t vl) {
|
|
return vluxei16(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_i64m1(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i32.i64(<vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]]
|
|
//
|
|
vint64m1_t test_vluxei32_v_i64m1(const int64_t *base, vuint32mf2_t bindex, size_t vl) {
|
|
return vluxei32(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_i64m2(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i32.i64(<vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]]
|
|
//
|
|
vint64m2_t test_vluxei32_v_i64m2(const int64_t *base, vuint32m1_t bindex, size_t vl) {
|
|
return vluxei32(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_i64m4(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i32.i64(<vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]]
|
|
//
|
|
vint64m4_t test_vluxei32_v_i64m4(const int64_t *base, vuint32m2_t bindex, size_t vl) {
|
|
return vluxei32(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_i64m8(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i32.i64(<vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]]
|
|
//
|
|
vint64m8_t test_vluxei32_v_i64m8(const int64_t *base, vuint32m4_t bindex, size_t vl) {
|
|
return vluxei32(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei64_v_i64m1(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]]
|
|
//
|
|
vint64m1_t test_vluxei64_v_i64m1(const int64_t *base, vuint64m1_t bindex, size_t vl) {
|
|
return vluxei64(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei64_v_i64m2(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]]
|
|
//
|
|
vint64m2_t test_vluxei64_v_i64m2(const int64_t *base, vuint64m2_t bindex, size_t vl) {
|
|
return vluxei64(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei64_v_i64m4(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]]
|
|
//
|
|
vint64m4_t test_vluxei64_v_i64m4(const int64_t *base, vuint64m4_t bindex, size_t vl) {
|
|
return vluxei64(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei64_v_i64m8(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]]
|
|
//
|
|
vint64m8_t test_vluxei64_v_i64m8(const int64_t *base, vuint64m8_t bindex, size_t vl) {
|
|
return vluxei64(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_u8mf8(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i8.i64(<vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
|
|
//
|
|
vuint8mf8_t test_vluxei8_v_u8mf8(const uint8_t *base, vuint8mf8_t bindex, size_t vl) {
|
|
return vluxei8(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_u8mf4(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i8.i64(<vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]]
|
|
//
|
|
vuint8mf4_t test_vluxei8_v_u8mf4(const uint8_t *base, vuint8mf4_t bindex, size_t vl) {
|
|
return vluxei8(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_u8mf2(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i8.i64(<vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]]
|
|
//
|
|
vuint8mf2_t test_vluxei8_v_u8mf2(const uint8_t *base, vuint8mf2_t bindex, size_t vl) {
|
|
return vluxei8(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_u8m1(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i8.i64(<vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]]
|
|
//
|
|
vuint8m1_t test_vluxei8_v_u8m1(const uint8_t *base, vuint8m1_t bindex, size_t vl) {
|
|
return vluxei8(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_u8m2(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vluxei.nxv16i8.nxv16i8.i64(<vscale x 16 x i8>* [[TMP0]], <vscale x 16 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP1]]
|
|
//
|
|
vuint8m2_t test_vluxei8_v_u8m2(const uint8_t *base, vuint8m2_t bindex, size_t vl) {
|
|
return vluxei8(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_u8m4(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vluxei.nxv32i8.nxv32i8.i64(<vscale x 32 x i8>* [[TMP0]], <vscale x 32 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP1]]
|
|
//
|
|
vuint8m4_t test_vluxei8_v_u8m4(const uint8_t *base, vuint8m4_t bindex, size_t vl) {
|
|
return vluxei8(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_u8m8(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vluxei.nxv64i8.nxv64i8.i64(<vscale x 64 x i8>* [[TMP0]], <vscale x 64 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP1]]
|
|
//
|
|
vuint8m8_t test_vluxei8_v_u8m8(const uint8_t *base, vuint8m8_t bindex, size_t vl) {
|
|
return vluxei8(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_u8mf8(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i16.i64(<vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
|
|
//
|
|
vuint8mf8_t test_vluxei16_v_u8mf8(const uint8_t *base, vuint16mf4_t bindex, size_t vl) {
|
|
return vluxei16(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_u8mf4(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i16.i64(<vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]]
|
|
//
|
|
vuint8mf4_t test_vluxei16_v_u8mf4(const uint8_t *base, vuint16mf2_t bindex, size_t vl) {
|
|
return vluxei16(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_u8mf2(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i16.i64(<vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]]
|
|
//
|
|
vuint8mf2_t test_vluxei16_v_u8mf2(const uint8_t *base, vuint16m1_t bindex, size_t vl) {
|
|
return vluxei16(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_u8m1(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i16.i64(<vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]]
|
|
//
|
|
vuint8m1_t test_vluxei16_v_u8m1(const uint8_t *base, vuint16m2_t bindex, size_t vl) {
|
|
return vluxei16(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_u8m2(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vluxei.nxv16i8.nxv16i16.i64(<vscale x 16 x i8>* [[TMP0]], <vscale x 16 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP1]]
|
|
//
|
|
vuint8m2_t test_vluxei16_v_u8m2(const uint8_t *base, vuint16m4_t bindex, size_t vl) {
|
|
return vluxei16(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_u8m4(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vluxei.nxv32i8.nxv32i16.i64(<vscale x 32 x i8>* [[TMP0]], <vscale x 32 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP1]]
|
|
//
|
|
vuint8m4_t test_vluxei16_v_u8m4(const uint8_t *base, vuint16m8_t bindex, size_t vl) {
|
|
return vluxei16(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_u8mf8(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i32.i64(<vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
|
|
//
|
|
vuint8mf8_t test_vluxei32_v_u8mf8(const uint8_t *base, vuint32mf2_t bindex, size_t vl) {
|
|
return vluxei32(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_u8mf4(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i32.i64(<vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]]
|
|
//
|
|
vuint8mf4_t test_vluxei32_v_u8mf4(const uint8_t *base, vuint32m1_t bindex, size_t vl) {
|
|
return vluxei32(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_u8mf2(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i32.i64(<vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]]
|
|
//
|
|
vuint8mf2_t test_vluxei32_v_u8mf2(const uint8_t *base, vuint32m2_t bindex, size_t vl) {
|
|
return vluxei32(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_u8m1(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i32.i64(<vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]]
|
|
//
|
|
vuint8m1_t test_vluxei32_v_u8m1(const uint8_t *base, vuint32m4_t bindex, size_t vl) {
|
|
return vluxei32(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_u8m2(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vluxei.nxv16i8.nxv16i32.i64(<vscale x 16 x i8>* [[TMP0]], <vscale x 16 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP1]]
|
|
//
|
|
vuint8m2_t test_vluxei32_v_u8m2(const uint8_t *base, vuint32m8_t bindex, size_t vl) {
|
|
return vluxei32(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei64_v_u8mf8(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i64.i64(<vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
|
|
//
|
|
vuint8mf8_t test_vluxei64_v_u8mf8(const uint8_t *base, vuint64m1_t bindex, size_t vl) {
|
|
return vluxei64(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei64_v_u8mf4(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i64.i64(<vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]]
|
|
//
|
|
vuint8mf4_t test_vluxei64_v_u8mf4(const uint8_t *base, vuint64m2_t bindex, size_t vl) {
|
|
return vluxei64(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei64_v_u8mf2(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i64.i64(<vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]]
|
|
//
|
|
vuint8mf2_t test_vluxei64_v_u8mf2(const uint8_t *base, vuint64m4_t bindex, size_t vl) {
|
|
return vluxei64(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei64_v_u8m1(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i64.i64(<vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]]
|
|
//
|
|
vuint8m1_t test_vluxei64_v_u8m1(const uint8_t *base, vuint64m8_t bindex, size_t vl) {
|
|
return vluxei64(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_u16mf4(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i8.i64(<vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]]
|
|
//
|
|
vuint16mf4_t test_vluxei8_v_u16mf4(const uint16_t *base, vuint8mf8_t bindex, size_t vl) {
|
|
return vluxei8(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_u16mf2(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i8.i64(<vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]]
|
|
//
|
|
vuint16mf2_t test_vluxei8_v_u16mf2(const uint16_t *base, vuint8mf4_t bindex, size_t vl) {
|
|
return vluxei8(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_u16m1(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i8.i64(<vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]]
|
|
//
|
|
vuint16m1_t test_vluxei8_v_u16m1(const uint16_t *base, vuint8mf2_t bindex, size_t vl) {
|
|
return vluxei8(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_u16m2(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i8.i64(<vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]]
|
|
//
|
|
vuint16m2_t test_vluxei8_v_u16m2(const uint16_t *base, vuint8m1_t bindex, size_t vl) {
|
|
return vluxei8(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_u16m4(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vluxei.nxv16i16.nxv16i8.i64(<vscale x 16 x i16>* [[TMP0]], <vscale x 16 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP1]]
|
|
//
|
|
vuint16m4_t test_vluxei8_v_u16m4(const uint16_t *base, vuint8m2_t bindex, size_t vl) {
|
|
return vluxei8(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_u16m8(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vluxei.nxv32i16.nxv32i8.i64(<vscale x 32 x i16>* [[TMP0]], <vscale x 32 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP1]]
|
|
//
|
|
vuint16m8_t test_vluxei8_v_u16m8(const uint16_t *base, vuint8m4_t bindex, size_t vl) {
|
|
return vluxei8(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_u16mf4(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i16.i64(<vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]]
|
|
//
|
|
vuint16mf4_t test_vluxei16_v_u16mf4(const uint16_t *base, vuint16mf4_t bindex, size_t vl) {
|
|
return vluxei16(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_u16mf2(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i16.i64(<vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]]
|
|
//
|
|
vuint16mf2_t test_vluxei16_v_u16mf2(const uint16_t *base, vuint16mf2_t bindex, size_t vl) {
|
|
return vluxei16(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_u16m1(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i16.i64(<vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]]
|
|
//
|
|
vuint16m1_t test_vluxei16_v_u16m1(const uint16_t *base, vuint16m1_t bindex, size_t vl) {
|
|
return vluxei16(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_u16m2(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i16.i64(<vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]]
|
|
//
|
|
vuint16m2_t test_vluxei16_v_u16m2(const uint16_t *base, vuint16m2_t bindex, size_t vl) {
|
|
return vluxei16(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_u16m4(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vluxei.nxv16i16.nxv16i16.i64(<vscale x 16 x i16>* [[TMP0]], <vscale x 16 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP1]]
|
|
//
|
|
vuint16m4_t test_vluxei16_v_u16m4(const uint16_t *base, vuint16m4_t bindex, size_t vl) {
|
|
return vluxei16(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_u16m8(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vluxei.nxv32i16.nxv32i16.i64(<vscale x 32 x i16>* [[TMP0]], <vscale x 32 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP1]]
|
|
//
|
|
vuint16m8_t test_vluxei16_v_u16m8(const uint16_t *base, vuint16m8_t bindex, size_t vl) {
|
|
return vluxei16(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_u16mf4(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i32.i64(<vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]]
|
|
//
|
|
vuint16mf4_t test_vluxei32_v_u16mf4(const uint16_t *base, vuint32mf2_t bindex, size_t vl) {
|
|
return vluxei32(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_u16mf2(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i32.i64(<vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]]
|
|
//
|
|
vuint16mf2_t test_vluxei32_v_u16mf2(const uint16_t *base, vuint32m1_t bindex, size_t vl) {
|
|
return vluxei32(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_u16m1(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i32.i64(<vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]]
|
|
//
|
|
vuint16m1_t test_vluxei32_v_u16m1(const uint16_t *base, vuint32m2_t bindex, size_t vl) {
|
|
return vluxei32(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_u16m2(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i32.i64(<vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]]
|
|
//
|
|
vuint16m2_t test_vluxei32_v_u16m2(const uint16_t *base, vuint32m4_t bindex, size_t vl) {
|
|
return vluxei32(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_u16m4(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vluxei.nxv16i16.nxv16i32.i64(<vscale x 16 x i16>* [[TMP0]], <vscale x 16 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP1]]
|
|
//
|
|
vuint16m4_t test_vluxei32_v_u16m4(const uint16_t *base, vuint32m8_t bindex, size_t vl) {
|
|
return vluxei32(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei64_v_u16mf4(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i64.i64(<vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]]
|
|
//
|
|
vuint16mf4_t test_vluxei64_v_u16mf4(const uint16_t *base, vuint64m1_t bindex, size_t vl) {
|
|
return vluxei64(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei64_v_u16mf2(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i64.i64(<vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]]
|
|
//
|
|
vuint16mf2_t test_vluxei64_v_u16mf2(const uint16_t *base, vuint64m2_t bindex, size_t vl) {
|
|
return vluxei64(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei64_v_u16m1(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i64.i64(<vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]]
|
|
//
|
|
vuint16m1_t test_vluxei64_v_u16m1(const uint16_t *base, vuint64m4_t bindex, size_t vl) {
|
|
return vluxei64(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei64_v_u16m2(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i64.i64(<vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]]
|
|
//
|
|
vuint16m2_t test_vluxei64_v_u16m2(const uint16_t *base, vuint64m8_t bindex, size_t vl) {
|
|
return vluxei64(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_u32mf2(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i8.i64(<vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
|
|
//
|
|
vuint32mf2_t test_vluxei8_v_u32mf2(const uint32_t *base, vuint8mf8_t bindex, size_t vl) {
|
|
return vluxei8(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_u32m1(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i8.i64(<vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]]
|
|
//
|
|
vuint32m1_t test_vluxei8_v_u32m1(const uint32_t *base, vuint8mf4_t bindex, size_t vl) {
|
|
return vluxei8(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_u32m2(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i8.i64(<vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]]
|
|
//
|
|
vuint32m2_t test_vluxei8_v_u32m2(const uint32_t *base, vuint8mf2_t bindex, size_t vl) {
|
|
return vluxei8(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_u32m4(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i8.i64(<vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]]
|
|
//
|
|
vuint32m4_t test_vluxei8_v_u32m4(const uint32_t *base, vuint8m1_t bindex, size_t vl) {
|
|
return vluxei8(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_u32m8(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vluxei.nxv16i32.nxv16i8.i64(<vscale x 16 x i32>* [[TMP0]], <vscale x 16 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP1]]
|
|
//
|
|
vuint32m8_t test_vluxei8_v_u32m8(const uint32_t *base, vuint8m2_t bindex, size_t vl) {
|
|
return vluxei8(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_u32mf2(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i16.i64(<vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
|
|
//
|
|
vuint32mf2_t test_vluxei16_v_u32mf2(const uint32_t *base, vuint16mf4_t bindex, size_t vl) {
|
|
return vluxei16(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_u32m1(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i16.i64(<vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]]
|
|
//
|
|
vuint32m1_t test_vluxei16_v_u32m1(const uint32_t *base, vuint16mf2_t bindex, size_t vl) {
|
|
return vluxei16(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_u32m2(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i16.i64(<vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]]
|
|
//
|
|
vuint32m2_t test_vluxei16_v_u32m2(const uint32_t *base, vuint16m1_t bindex, size_t vl) {
|
|
return vluxei16(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_u32m4(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i16.i64(<vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]]
|
|
//
|
|
vuint32m4_t test_vluxei16_v_u32m4(const uint32_t *base, vuint16m2_t bindex, size_t vl) {
|
|
return vluxei16(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_u32m8(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vluxei.nxv16i32.nxv16i16.i64(<vscale x 16 x i32>* [[TMP0]], <vscale x 16 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP1]]
|
|
//
|
|
vuint32m8_t test_vluxei16_v_u32m8(const uint32_t *base, vuint16m4_t bindex, size_t vl) {
|
|
return vluxei16(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_u32mf2(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i32.i64(<vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
|
|
//
|
|
vuint32mf2_t test_vluxei32_v_u32mf2(const uint32_t *base, vuint32mf2_t bindex, size_t vl) {
|
|
return vluxei32(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_u32m1(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i32.i64(<vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]]
|
|
//
|
|
vuint32m1_t test_vluxei32_v_u32m1(const uint32_t *base, vuint32m1_t bindex, size_t vl) {
|
|
return vluxei32(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_u32m2(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i32.i64(<vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]]
|
|
//
|
|
vuint32m2_t test_vluxei32_v_u32m2(const uint32_t *base, vuint32m2_t bindex, size_t vl) {
|
|
return vluxei32(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_u32m4(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i32.i64(<vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]]
|
|
//
|
|
vuint32m4_t test_vluxei32_v_u32m4(const uint32_t *base, vuint32m4_t bindex, size_t vl) {
|
|
return vluxei32(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_u32m8(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vluxei.nxv16i32.nxv16i32.i64(<vscale x 16 x i32>* [[TMP0]], <vscale x 16 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP1]]
|
|
//
|
|
vuint32m8_t test_vluxei32_v_u32m8(const uint32_t *base, vuint32m8_t bindex, size_t vl) {
|
|
return vluxei32(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei64_v_u32mf2(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i64.i64(<vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
|
|
//
|
|
vuint32mf2_t test_vluxei64_v_u32mf2(const uint32_t *base, vuint64m1_t bindex, size_t vl) {
|
|
return vluxei64(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei64_v_u32m1(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i64.i64(<vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]]
|
|
//
|
|
vuint32m1_t test_vluxei64_v_u32m1(const uint32_t *base, vuint64m2_t bindex, size_t vl) {
|
|
return vluxei64(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei64_v_u32m2(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i64.i64(<vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]]
|
|
//
|
|
vuint32m2_t test_vluxei64_v_u32m2(const uint32_t *base, vuint64m4_t bindex, size_t vl) {
|
|
return vluxei64(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei64_v_u32m4(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i64.i64(<vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]]
|
|
//
|
|
vuint32m4_t test_vluxei64_v_u32m4(const uint32_t *base, vuint64m8_t bindex, size_t vl) {
|
|
return vluxei64(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_u64m1(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i8.i64(<vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]]
|
|
//
|
|
vuint64m1_t test_vluxei8_v_u64m1(const uint64_t *base, vuint8mf8_t bindex, size_t vl) {
|
|
return vluxei8(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_u64m2(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i8.i64(<vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]]
|
|
//
|
|
vuint64m2_t test_vluxei8_v_u64m2(const uint64_t *base, vuint8mf4_t bindex, size_t vl) {
|
|
return vluxei8(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_u64m4(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i8.i64(<vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]]
|
|
//
|
|
vuint64m4_t test_vluxei8_v_u64m4(const uint64_t *base, vuint8mf2_t bindex, size_t vl) {
|
|
return vluxei8(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_u64m8(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i8.i64(<vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]]
|
|
//
|
|
vuint64m8_t test_vluxei8_v_u64m8(const uint64_t *base, vuint8m1_t bindex, size_t vl) {
|
|
return vluxei8(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_u64m1(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i16.i64(<vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]]
|
|
//
|
|
vuint64m1_t test_vluxei16_v_u64m1(const uint64_t *base, vuint16mf4_t bindex, size_t vl) {
|
|
return vluxei16(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_u64m2(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i16.i64(<vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]]
|
|
//
|
|
vuint64m2_t test_vluxei16_v_u64m2(const uint64_t *base, vuint16mf2_t bindex, size_t vl) {
|
|
return vluxei16(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_u64m4(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i16.i64(<vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]]
|
|
//
|
|
vuint64m4_t test_vluxei16_v_u64m4(const uint64_t *base, vuint16m1_t bindex, size_t vl) {
|
|
return vluxei16(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_u64m8(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i16.i64(<vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]]
|
|
//
|
|
vuint64m8_t test_vluxei16_v_u64m8(const uint64_t *base, vuint16m2_t bindex, size_t vl) {
|
|
return vluxei16(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_u64m1(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i32.i64(<vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]]
|
|
//
|
|
vuint64m1_t test_vluxei32_v_u64m1(const uint64_t *base, vuint32mf2_t bindex, size_t vl) {
|
|
return vluxei32(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_u64m2(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i32.i64(<vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]]
|
|
//
|
|
vuint64m2_t test_vluxei32_v_u64m2(const uint64_t *base, vuint32m1_t bindex, size_t vl) {
|
|
return vluxei32(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_u64m4(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i32.i64(<vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]]
|
|
//
|
|
vuint64m4_t test_vluxei32_v_u64m4(const uint64_t *base, vuint32m2_t bindex, size_t vl) {
|
|
return vluxei32(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_u64m8(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i32.i64(<vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]]
|
|
//
|
|
vuint64m8_t test_vluxei32_v_u64m8(const uint64_t *base, vuint32m4_t bindex, size_t vl) {
|
|
return vluxei32(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei64_v_u64m1(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]]
|
|
//
|
|
vuint64m1_t test_vluxei64_v_u64m1(const uint64_t *base, vuint64m1_t bindex, size_t vl) {
|
|
return vluxei64(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei64_v_u64m2(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i64.i64(<vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]]
|
|
//
|
|
vuint64m2_t test_vluxei64_v_u64m2(const uint64_t *base, vuint64m2_t bindex, size_t vl) {
|
|
return vluxei64(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei64_v_u64m4(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i64.i64(<vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]]
|
|
//
|
|
vuint64m4_t test_vluxei64_v_u64m4(const uint64_t *base, vuint64m4_t bindex, size_t vl) {
|
|
return vluxei64(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei64_v_u64m8(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i64.i64(<vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]]
|
|
//
|
|
vuint64m8_t test_vluxei64_v_u64m8(const uint64_t *base, vuint64m8_t bindex, size_t vl) {
|
|
return vluxei64(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_f32mf2(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.nxv1i8.i64(<vscale x 1 x float>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]]
|
|
//
|
|
vfloat32mf2_t test_vluxei8_v_f32mf2(const float *base, vuint8mf8_t bindex, size_t vl) {
|
|
return vluxei8(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_f32m1(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 2 x float>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.nxv2i8.i64(<vscale x 2 x float>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP1]]
|
|
//
|
|
vfloat32m1_t test_vluxei8_v_f32m1(const float *base, vuint8mf4_t bindex, size_t vl) {
|
|
return vluxei8(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_f32m2(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 4 x float>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.nxv4i8.i64(<vscale x 4 x float>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP1]]
|
|
//
|
|
vfloat32m2_t test_vluxei8_v_f32m2(const float *base, vuint8mf2_t bindex, size_t vl) {
|
|
return vluxei8(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_f32m4(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 8 x float>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.nxv8i8.i64(<vscale x 8 x float>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP1]]
|
|
//
|
|
vfloat32m4_t test_vluxei8_v_f32m4(const float *base, vuint8m1_t bindex, size_t vl) {
|
|
return vluxei8(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_f32m8(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 16 x float>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x float> @llvm.riscv.vluxei.nxv16f32.nxv16i8.i64(<vscale x 16 x float>* [[TMP0]], <vscale x 16 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP1]]
|
|
//
|
|
vfloat32m8_t test_vluxei8_v_f32m8(const float *base, vuint8m2_t bindex, size_t vl) {
|
|
return vluxei8(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_f32mf2(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.nxv1i16.i64(<vscale x 1 x float>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]]
|
|
//
|
|
vfloat32mf2_t test_vluxei16_v_f32mf2(const float *base, vuint16mf4_t bindex, size_t vl) {
|
|
return vluxei16(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_f32m1(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 2 x float>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.nxv2i16.i64(<vscale x 2 x float>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP1]]
|
|
//
|
|
vfloat32m1_t test_vluxei16_v_f32m1(const float *base, vuint16mf2_t bindex, size_t vl) {
|
|
return vluxei16(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_f32m2(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 4 x float>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.nxv4i16.i64(<vscale x 4 x float>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP1]]
|
|
//
|
|
vfloat32m2_t test_vluxei16_v_f32m2(const float *base, vuint16m1_t bindex, size_t vl) {
|
|
return vluxei16(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_f32m4(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 8 x float>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.nxv8i16.i64(<vscale x 8 x float>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP1]]
|
|
//
|
|
vfloat32m4_t test_vluxei16_v_f32m4(const float *base, vuint16m2_t bindex, size_t vl) {
|
|
return vluxei16(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_f32m8(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 16 x float>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x float> @llvm.riscv.vluxei.nxv16f32.nxv16i16.i64(<vscale x 16 x float>* [[TMP0]], <vscale x 16 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP1]]
|
|
//
|
|
vfloat32m8_t test_vluxei16_v_f32m8(const float *base, vuint16m4_t bindex, size_t vl) {
|
|
return vluxei16(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_f32mf2(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.nxv1i32.i64(<vscale x 1 x float>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]]
|
|
//
|
|
vfloat32mf2_t test_vluxei32_v_f32mf2(const float *base, vuint32mf2_t bindex, size_t vl) {
|
|
return vluxei32(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_f32m1(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 2 x float>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.nxv2i32.i64(<vscale x 2 x float>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP1]]
|
|
//
|
|
vfloat32m1_t test_vluxei32_v_f32m1(const float *base, vuint32m1_t bindex, size_t vl) {
|
|
return vluxei32(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_f32m2(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 4 x float>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.nxv4i32.i64(<vscale x 4 x float>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP1]]
|
|
//
|
|
vfloat32m2_t test_vluxei32_v_f32m2(const float *base, vuint32m2_t bindex, size_t vl) {
|
|
return vluxei32(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_f32m4(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 8 x float>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.nxv8i32.i64(<vscale x 8 x float>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP1]]
|
|
//
|
|
vfloat32m4_t test_vluxei32_v_f32m4(const float *base, vuint32m4_t bindex, size_t vl) {
|
|
return vluxei32(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_f32m8(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 16 x float>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x float> @llvm.riscv.vluxei.nxv16f32.nxv16i32.i64(<vscale x 16 x float>* [[TMP0]], <vscale x 16 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP1]]
|
|
//
|
|
vfloat32m8_t test_vluxei32_v_f32m8(const float *base, vuint32m8_t bindex, size_t vl) {
|
|
return vluxei32(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei64_v_f32mf2(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.nxv1i64.i64(<vscale x 1 x float>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]]
|
|
//
|
|
vfloat32mf2_t test_vluxei64_v_f32mf2(const float *base, vuint64m1_t bindex, size_t vl) {
|
|
return vluxei64(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei64_v_f32m1(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 2 x float>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.nxv2i64.i64(<vscale x 2 x float>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP1]]
|
|
//
|
|
vfloat32m1_t test_vluxei64_v_f32m1(const float *base, vuint64m2_t bindex, size_t vl) {
|
|
return vluxei64(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei64_v_f32m2(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 4 x float>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.nxv4i64.i64(<vscale x 4 x float>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP1]]
|
|
//
|
|
vfloat32m2_t test_vluxei64_v_f32m2(const float *base, vuint64m4_t bindex, size_t vl) {
|
|
return vluxei64(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei64_v_f32m4(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 8 x float>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.nxv8i64.i64(<vscale x 8 x float>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP1]]
|
|
//
|
|
vfloat32m4_t test_vluxei64_v_f32m4(const float *base, vuint64m8_t bindex, size_t vl) {
|
|
return vluxei64(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_f64m1(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 1 x double>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.nxv1i8.i64(<vscale x 1 x double>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP1]]
|
|
//
|
|
vfloat64m1_t test_vluxei8_v_f64m1(const double *base, vuint8mf8_t bindex, size_t vl) {
|
|
return vluxei8(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_f64m2(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 2 x double>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.nxv2i8.i64(<vscale x 2 x double>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP1]]
|
|
//
|
|
vfloat64m2_t test_vluxei8_v_f64m2(const double *base, vuint8mf4_t bindex, size_t vl) {
|
|
return vluxei8(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_f64m4(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 4 x double>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x double> @llvm.riscv.vluxei.nxv4f64.nxv4i8.i64(<vscale x 4 x double>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP1]]
|
|
//
|
|
vfloat64m4_t test_vluxei8_v_f64m4(const double *base, vuint8mf2_t bindex, size_t vl) {
|
|
return vluxei8(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_f64m8(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 8 x double>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x double> @llvm.riscv.vluxei.nxv8f64.nxv8i8.i64(<vscale x 8 x double>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP1]]
|
|
//
|
|
vfloat64m8_t test_vluxei8_v_f64m8(const double *base, vuint8m1_t bindex, size_t vl) {
|
|
return vluxei8(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_f64m1(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 1 x double>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.nxv1i16.i64(<vscale x 1 x double>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP1]]
|
|
//
|
|
vfloat64m1_t test_vluxei16_v_f64m1(const double *base, vuint16mf4_t bindex, size_t vl) {
|
|
return vluxei16(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_f64m2(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 2 x double>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.nxv2i16.i64(<vscale x 2 x double>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP1]]
|
|
//
|
|
vfloat64m2_t test_vluxei16_v_f64m2(const double *base, vuint16mf2_t bindex, size_t vl) {
|
|
return vluxei16(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_f64m4(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 4 x double>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x double> @llvm.riscv.vluxei.nxv4f64.nxv4i16.i64(<vscale x 4 x double>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP1]]
|
|
//
|
|
vfloat64m4_t test_vluxei16_v_f64m4(const double *base, vuint16m1_t bindex, size_t vl) {
|
|
return vluxei16(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_f64m8(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 8 x double>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x double> @llvm.riscv.vluxei.nxv8f64.nxv8i16.i64(<vscale x 8 x double>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP1]]
|
|
//
|
|
vfloat64m8_t test_vluxei16_v_f64m8(const double *base, vuint16m2_t bindex, size_t vl) {
|
|
return vluxei16(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_f64m1(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 1 x double>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.nxv1i32.i64(<vscale x 1 x double>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP1]]
|
|
//
|
|
vfloat64m1_t test_vluxei32_v_f64m1(const double *base, vuint32mf2_t bindex, size_t vl) {
|
|
return vluxei32(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_f64m2(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 2 x double>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.nxv2i32.i64(<vscale x 2 x double>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP1]]
|
|
//
|
|
vfloat64m2_t test_vluxei32_v_f64m2(const double *base, vuint32m1_t bindex, size_t vl) {
|
|
return vluxei32(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_f64m4(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 4 x double>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x double> @llvm.riscv.vluxei.nxv4f64.nxv4i32.i64(<vscale x 4 x double>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP1]]
|
|
//
|
|
vfloat64m4_t test_vluxei32_v_f64m4(const double *base, vuint32m2_t bindex, size_t vl) {
|
|
return vluxei32(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_f64m8(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 8 x double>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x double> @llvm.riscv.vluxei.nxv8f64.nxv8i32.i64(<vscale x 8 x double>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP1]]
|
|
//
|
|
vfloat64m8_t test_vluxei32_v_f64m8(const double *base, vuint32m4_t bindex, size_t vl) {
|
|
return vluxei32(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei64_v_f64m1(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 1 x double>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.nxv1i64.i64(<vscale x 1 x double>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP1]]
|
|
//
|
|
vfloat64m1_t test_vluxei64_v_f64m1(const double *base, vuint64m1_t bindex, size_t vl) {
|
|
return vluxei64(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei64_v_f64m2(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 2 x double>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.nxv2i64.i64(<vscale x 2 x double>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP1]]
|
|
//
|
|
vfloat64m2_t test_vluxei64_v_f64m2(const double *base, vuint64m2_t bindex, size_t vl) {
|
|
return vluxei64(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei64_v_f64m4(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 4 x double>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x double> @llvm.riscv.vluxei.nxv4f64.nxv4i64.i64(<vscale x 4 x double>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP1]]
|
|
//
|
|
vfloat64m4_t test_vluxei64_v_f64m4(const double *base, vuint64m4_t bindex, size_t vl) {
|
|
return vluxei64(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei64_v_f64m8(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 8 x double>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x double> @llvm.riscv.vluxei.nxv8f64.nxv8i64.i64(<vscale x 8 x double>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], i64 [[VL:%.*]])
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP1]]
|
|
//
|
|
vfloat64m8_t test_vluxei64_v_f64m8(const double *base, vuint64m8_t bindex, size_t vl) {
|
|
return vluxei64(base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_i8mf8_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vluxei.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
|
|
//
|
|
vint8mf8_t test_vluxei8_v_i8mf8_m(vbool64_t mask, vint8mf8_t maskedoff, const int8_t *base, vuint8mf8_t bindex, size_t vl) {
|
|
return vluxei8(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_i8mf4_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vluxei.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]]
|
|
//
|
|
vint8mf4_t test_vluxei8_v_i8mf4_m(vbool32_t mask, vint8mf4_t maskedoff, const int8_t *base, vuint8mf4_t bindex, size_t vl) {
|
|
return vluxei8(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_i8mf2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vluxei.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]]
|
|
//
|
|
vint8mf2_t test_vluxei8_v_i8mf2_m(vbool16_t mask, vint8mf2_t maskedoff, const int8_t *base, vuint8mf2_t bindex, size_t vl) {
|
|
return vluxei8(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_i8m1_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vluxei.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]]
|
|
//
|
|
vint8m1_t test_vluxei8_v_i8m1_m(vbool8_t mask, vint8m1_t maskedoff, const int8_t *base, vuint8m1_t bindex, size_t vl) {
|
|
return vluxei8(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_i8m2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vluxei.mask.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x i8>* [[TMP0]], <vscale x 16 x i8> [[BINDEX:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP1]]
|
|
//
|
|
vint8m2_t test_vluxei8_v_i8m2_m(vbool4_t mask, vint8m2_t maskedoff, const int8_t *base, vuint8m2_t bindex, size_t vl) {
|
|
return vluxei8(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_i8m4_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vluxei.mask.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x i8>* [[TMP0]], <vscale x 32 x i8> [[BINDEX:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP1]]
|
|
//
|
|
vint8m4_t test_vluxei8_v_i8m4_m(vbool2_t mask, vint8m4_t maskedoff, const int8_t *base, vuint8m4_t bindex, size_t vl) {
|
|
return vluxei8(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_i8m8_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vluxei.mask.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[MASKEDOFF:%.*]], <vscale x 64 x i8>* [[TMP0]], <vscale x 64 x i8> [[BINDEX:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP1]]
|
|
//
|
|
vint8m8_t test_vluxei8_v_i8m8_m(vbool1_t mask, vint8m8_t maskedoff, const int8_t *base, vuint8m8_t bindex, size_t vl) {
|
|
return vluxei8(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_i8mf8_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vluxei.mask.nxv1i8.nxv1i16.i64(<vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
|
|
//
|
|
vint8mf8_t test_vluxei16_v_i8mf8_m(vbool64_t mask, vint8mf8_t maskedoff, const int8_t *base, vuint16mf4_t bindex, size_t vl) {
|
|
return vluxei16(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_i8mf4_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vluxei.mask.nxv2i8.nxv2i16.i64(<vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]]
|
|
//
|
|
vint8mf4_t test_vluxei16_v_i8mf4_m(vbool32_t mask, vint8mf4_t maskedoff, const int8_t *base, vuint16mf2_t bindex, size_t vl) {
|
|
return vluxei16(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_i8mf2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vluxei.mask.nxv4i8.nxv4i16.i64(<vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]]
|
|
//
|
|
vint8mf2_t test_vluxei16_v_i8mf2_m(vbool16_t mask, vint8mf2_t maskedoff, const int8_t *base, vuint16m1_t bindex, size_t vl) {
|
|
return vluxei16(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_i8m1_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vluxei.mask.nxv8i8.nxv8i16.i64(<vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]]
|
|
//
|
|
vint8m1_t test_vluxei16_v_i8m1_m(vbool8_t mask, vint8m1_t maskedoff, const int8_t *base, vuint16m2_t bindex, size_t vl) {
|
|
return vluxei16(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_i8m2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vluxei.mask.nxv16i8.nxv16i16.i64(<vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x i8>* [[TMP0]], <vscale x 16 x i16> [[BINDEX:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP1]]
|
|
//
|
|
vint8m2_t test_vluxei16_v_i8m2_m(vbool4_t mask, vint8m2_t maskedoff, const int8_t *base, vuint16m4_t bindex, size_t vl) {
|
|
return vluxei16(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_i8m4_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vluxei.mask.nxv32i8.nxv32i16.i64(<vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x i8>* [[TMP0]], <vscale x 32 x i16> [[BINDEX:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP1]]
|
|
//
|
|
vint8m4_t test_vluxei16_v_i8m4_m(vbool2_t mask, vint8m4_t maskedoff, const int8_t *base, vuint16m8_t bindex, size_t vl) {
|
|
return vluxei16(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_i8mf8_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vluxei.mask.nxv1i8.nxv1i32.i64(<vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
|
|
//
|
|
vint8mf8_t test_vluxei32_v_i8mf8_m(vbool64_t mask, vint8mf8_t maskedoff, const int8_t *base, vuint32mf2_t bindex, size_t vl) {
|
|
return vluxei32(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_i8mf4_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vluxei.mask.nxv2i8.nxv2i32.i64(<vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]]
|
|
//
|
|
vint8mf4_t test_vluxei32_v_i8mf4_m(vbool32_t mask, vint8mf4_t maskedoff, const int8_t *base, vuint32m1_t bindex, size_t vl) {
|
|
return vluxei32(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_i8mf2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vluxei.mask.nxv4i8.nxv4i32.i64(<vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]]
|
|
//
|
|
vint8mf2_t test_vluxei32_v_i8mf2_m(vbool16_t mask, vint8mf2_t maskedoff, const int8_t *base, vuint32m2_t bindex, size_t vl) {
|
|
return vluxei32(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_i8m1_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vluxei.mask.nxv8i8.nxv8i32.i64(<vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]]
|
|
//
|
|
vint8m1_t test_vluxei32_v_i8m1_m(vbool8_t mask, vint8m1_t maskedoff, const int8_t *base, vuint32m4_t bindex, size_t vl) {
|
|
return vluxei32(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_i8m2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vluxei.mask.nxv16i8.nxv16i32.i64(<vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x i8>* [[TMP0]], <vscale x 16 x i32> [[BINDEX:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP1]]
|
|
//
|
|
vint8m2_t test_vluxei32_v_i8m2_m(vbool4_t mask, vint8m2_t maskedoff, const int8_t *base, vuint32m8_t bindex, size_t vl) {
|
|
return vluxei32(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei64_v_i8mf8_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vluxei.mask.nxv1i8.nxv1i64.i64(<vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
|
|
//
|
|
vint8mf8_t test_vluxei64_v_i8mf8_m(vbool64_t mask, vint8mf8_t maskedoff, const int8_t *base, vuint64m1_t bindex, size_t vl) {
|
|
return vluxei64(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei64_v_i8mf4_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vluxei.mask.nxv2i8.nxv2i64.i64(<vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]]
|
|
//
|
|
vint8mf4_t test_vluxei64_v_i8mf4_m(vbool32_t mask, vint8mf4_t maskedoff, const int8_t *base, vuint64m2_t bindex, size_t vl) {
|
|
return vluxei64(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei64_v_i8mf2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vluxei.mask.nxv4i8.nxv4i64.i64(<vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]]
|
|
//
|
|
vint8mf2_t test_vluxei64_v_i8mf2_m(vbool16_t mask, vint8mf2_t maskedoff, const int8_t *base, vuint64m4_t bindex, size_t vl) {
|
|
return vluxei64(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei64_v_i8m1_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vluxei.mask.nxv8i8.nxv8i64.i64(<vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]]
|
|
//
|
|
vint8m1_t test_vluxei64_v_i8m1_m(vbool8_t mask, vint8m1_t maskedoff, const int8_t *base, vuint64m8_t bindex, size_t vl) {
|
|
return vluxei64(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_i16mf4_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vluxei.mask.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]]
|
|
//
|
|
vint16mf4_t test_vluxei8_v_i16mf4_m(vbool64_t mask, vint16mf4_t maskedoff, const int16_t *base, vuint8mf8_t bindex, size_t vl) {
|
|
return vluxei8(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_i16mf2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vluxei.mask.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]]
|
|
//
|
|
vint16mf2_t test_vluxei8_v_i16mf2_m(vbool32_t mask, vint16mf2_t maskedoff, const int16_t *base, vuint8mf4_t bindex, size_t vl) {
|
|
return vluxei8(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_i16m1_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vluxei.mask.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]]
|
|
//
|
|
vint16m1_t test_vluxei8_v_i16m1_m(vbool16_t mask, vint16m1_t maskedoff, const int16_t *base, vuint8mf2_t bindex, size_t vl) {
|
|
return vluxei8(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_i16m2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vluxei.mask.nxv8i16.nxv8i8.i64(<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]]
|
|
//
|
|
vint16m2_t test_vluxei8_v_i16m2_m(vbool8_t mask, vint16m2_t maskedoff, const int16_t *base, vuint8m1_t bindex, size_t vl) {
|
|
return vluxei8(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_i16m4_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vluxei.mask.nxv16i16.nxv16i8.i64(<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16>* [[TMP0]], <vscale x 16 x i8> [[BINDEX:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP1]]
|
|
//
|
|
vint16m4_t test_vluxei8_v_i16m4_m(vbool4_t mask, vint16m4_t maskedoff, const int16_t *base, vuint8m2_t bindex, size_t vl) {
|
|
return vluxei8(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_i16m8_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vluxei.mask.nxv32i16.nxv32i8.i64(<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i16>* [[TMP0]], <vscale x 32 x i8> [[BINDEX:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP1]]
|
|
//
|
|
vint16m8_t test_vluxei8_v_i16m8_m(vbool2_t mask, vint16m8_t maskedoff, const int16_t *base, vuint8m4_t bindex, size_t vl) {
|
|
return vluxei8(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_i16mf4_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vluxei.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]]
|
|
//
|
|
vint16mf4_t test_vluxei16_v_i16mf4_m(vbool64_t mask, vint16mf4_t maskedoff, const int16_t *base, vuint16mf4_t bindex, size_t vl) {
|
|
return vluxei16(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_i16mf2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vluxei.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]]
|
|
//
|
|
vint16mf2_t test_vluxei16_v_i16mf2_m(vbool32_t mask, vint16mf2_t maskedoff, const int16_t *base, vuint16mf2_t bindex, size_t vl) {
|
|
return vluxei16(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_i16m1_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vluxei.mask.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]]
|
|
//
|
|
vint16m1_t test_vluxei16_v_i16m1_m(vbool16_t mask, vint16m1_t maskedoff, const int16_t *base, vuint16m1_t bindex, size_t vl) {
|
|
return vluxei16(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_i16m2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vluxei.mask.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]]
|
|
//
|
|
vint16m2_t test_vluxei16_v_i16m2_m(vbool8_t mask, vint16m2_t maskedoff, const int16_t *base, vuint16m2_t bindex, size_t vl) {
|
|
return vluxei16(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_i16m4_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vluxei.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16>* [[TMP0]], <vscale x 16 x i16> [[BINDEX:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP1]]
|
|
//
|
|
vint16m4_t test_vluxei16_v_i16m4_m(vbool4_t mask, vint16m4_t maskedoff, const int16_t *base, vuint16m4_t bindex, size_t vl) {
|
|
return vluxei16(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_i16m8_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vluxei.mask.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i16>* [[TMP0]], <vscale x 32 x i16> [[BINDEX:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP1]]
|
|
//
|
|
vint16m8_t test_vluxei16_v_i16m8_m(vbool2_t mask, vint16m8_t maskedoff, const int16_t *base, vuint16m8_t bindex, size_t vl) {
|
|
return vluxei16(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_i16mf4_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vluxei.mask.nxv1i16.nxv1i32.i64(<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]]
|
|
//
|
|
vint16mf4_t test_vluxei32_v_i16mf4_m(vbool64_t mask, vint16mf4_t maskedoff, const int16_t *base, vuint32mf2_t bindex, size_t vl) {
|
|
return vluxei32(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_i16mf2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vluxei.mask.nxv2i16.nxv2i32.i64(<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]]
|
|
//
|
|
vint16mf2_t test_vluxei32_v_i16mf2_m(vbool32_t mask, vint16mf2_t maskedoff, const int16_t *base, vuint32m1_t bindex, size_t vl) {
|
|
return vluxei32(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_i16m1_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vluxei.mask.nxv4i16.nxv4i32.i64(<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]]
|
|
//
|
|
vint16m1_t test_vluxei32_v_i16m1_m(vbool16_t mask, vint16m1_t maskedoff, const int16_t *base, vuint32m2_t bindex, size_t vl) {
|
|
return vluxei32(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_i16m2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vluxei.mask.nxv8i16.nxv8i32.i64(<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]]
|
|
//
|
|
vint16m2_t test_vluxei32_v_i16m2_m(vbool8_t mask, vint16m2_t maskedoff, const int16_t *base, vuint32m4_t bindex, size_t vl) {
|
|
return vluxei32(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_i16m4_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vluxei.mask.nxv16i16.nxv16i32.i64(<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16>* [[TMP0]], <vscale x 16 x i32> [[BINDEX:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP1]]
|
|
//
|
|
vint16m4_t test_vluxei32_v_i16m4_m(vbool4_t mask, vint16m4_t maskedoff, const int16_t *base, vuint32m8_t bindex, size_t vl) {
|
|
return vluxei32(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei64_v_i16mf4_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vluxei.mask.nxv1i16.nxv1i64.i64(<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]]
|
|
//
|
|
vint16mf4_t test_vluxei64_v_i16mf4_m(vbool64_t mask, vint16mf4_t maskedoff, const int16_t *base, vuint64m1_t bindex, size_t vl) {
|
|
return vluxei64(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei64_v_i16mf2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vluxei.mask.nxv2i16.nxv2i64.i64(<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]]
|
|
//
|
|
vint16mf2_t test_vluxei64_v_i16mf2_m(vbool32_t mask, vint16mf2_t maskedoff, const int16_t *base, vuint64m2_t bindex, size_t vl) {
|
|
return vluxei64(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei64_v_i16m1_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vluxei.mask.nxv4i16.nxv4i64.i64(<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]]
|
|
//
|
|
vint16m1_t test_vluxei64_v_i16m1_m(vbool16_t mask, vint16m1_t maskedoff, const int16_t *base, vuint64m4_t bindex, size_t vl) {
|
|
return vluxei64(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei64_v_i16m2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vluxei.mask.nxv8i16.nxv8i64.i64(<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]]
|
|
//
|
|
vint16m2_t test_vluxei64_v_i16m2_m(vbool8_t mask, vint16m2_t maskedoff, const int16_t *base, vuint64m8_t bindex, size_t vl) {
|
|
return vluxei64(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_i32mf2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vluxei.mask.nxv1i32.nxv1i8.i64(<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
|
|
//
|
|
vint32mf2_t test_vluxei8_v_i32mf2_m(vbool64_t mask, vint32mf2_t maskedoff, const int32_t *base, vuint8mf8_t bindex, size_t vl) {
|
|
return vluxei8(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_i32m1_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vluxei.mask.nxv2i32.nxv2i8.i64(<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]]
|
|
//
|
|
vint32m1_t test_vluxei8_v_i32m1_m(vbool32_t mask, vint32m1_t maskedoff, const int32_t *base, vuint8mf4_t bindex, size_t vl) {
|
|
return vluxei8(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_i32m2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vluxei.mask.nxv4i32.nxv4i8.i64(<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]]
|
|
//
|
|
vint32m2_t test_vluxei8_v_i32m2_m(vbool16_t mask, vint32m2_t maskedoff, const int32_t *base, vuint8mf2_t bindex, size_t vl) {
|
|
return vluxei8(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_i32m4_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vluxei.mask.nxv8i32.nxv8i8.i64(<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]]
|
|
//
|
|
vint32m4_t test_vluxei8_v_i32m4_m(vbool8_t mask, vint32m4_t maskedoff, const int32_t *base, vuint8m1_t bindex, size_t vl) {
|
|
return vluxei8(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_i32m8_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vluxei.mask.nxv16i32.nxv16i8.i64(<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32>* [[TMP0]], <vscale x 16 x i8> [[BINDEX:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP1]]
|
|
//
|
|
vint32m8_t test_vluxei8_v_i32m8_m(vbool4_t mask, vint32m8_t maskedoff, const int32_t *base, vuint8m2_t bindex, size_t vl) {
|
|
return vluxei8(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_i32mf2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vluxei.mask.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
|
|
//
|
|
vint32mf2_t test_vluxei16_v_i32mf2_m(vbool64_t mask, vint32mf2_t maskedoff, const int32_t *base, vuint16mf4_t bindex, size_t vl) {
|
|
return vluxei16(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_i32m1_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vluxei.mask.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]]
|
|
//
|
|
vint32m1_t test_vluxei16_v_i32m1_m(vbool32_t mask, vint32m1_t maskedoff, const int32_t *base, vuint16mf2_t bindex, size_t vl) {
|
|
return vluxei16(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_i32m2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vluxei.mask.nxv4i32.nxv4i16.i64(<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]]
|
|
//
|
|
vint32m2_t test_vluxei16_v_i32m2_m(vbool16_t mask, vint32m2_t maskedoff, const int32_t *base, vuint16m1_t bindex, size_t vl) {
|
|
return vluxei16(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_i32m4_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vluxei.mask.nxv8i32.nxv8i16.i64(<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]]
|
|
//
|
|
vint32m4_t test_vluxei16_v_i32m4_m(vbool8_t mask, vint32m4_t maskedoff, const int32_t *base, vuint16m2_t bindex, size_t vl) {
|
|
return vluxei16(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_i32m8_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vluxei.mask.nxv16i32.nxv16i16.i64(<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32>* [[TMP0]], <vscale x 16 x i16> [[BINDEX:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP1]]
|
|
//
|
|
vint32m8_t test_vluxei16_v_i32m8_m(vbool4_t mask, vint32m8_t maskedoff, const int32_t *base, vuint16m4_t bindex, size_t vl) {
|
|
return vluxei16(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_i32mf2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vluxei.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
|
|
//
|
|
vint32mf2_t test_vluxei32_v_i32mf2_m(vbool64_t mask, vint32mf2_t maskedoff, const int32_t *base, vuint32mf2_t bindex, size_t vl) {
|
|
return vluxei32(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_i32m1_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vluxei.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]]
|
|
//
|
|
vint32m1_t test_vluxei32_v_i32m1_m(vbool32_t mask, vint32m1_t maskedoff, const int32_t *base, vuint32m1_t bindex, size_t vl) {
|
|
return vluxei32(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_i32m2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vluxei.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]]
|
|
//
|
|
vint32m2_t test_vluxei32_v_i32m2_m(vbool16_t mask, vint32m2_t maskedoff, const int32_t *base, vuint32m2_t bindex, size_t vl) {
|
|
return vluxei32(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_i32m4_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vluxei.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]]
|
|
//
|
|
vint32m4_t test_vluxei32_v_i32m4_m(vbool8_t mask, vint32m4_t maskedoff, const int32_t *base, vuint32m4_t bindex, size_t vl) {
|
|
return vluxei32(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_i32m8_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vluxei.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32>* [[TMP0]], <vscale x 16 x i32> [[BINDEX:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP1]]
|
|
//
|
|
vint32m8_t test_vluxei32_v_i32m8_m(vbool4_t mask, vint32m8_t maskedoff, const int32_t *base, vuint32m8_t bindex, size_t vl) {
|
|
return vluxei32(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei64_v_i32mf2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vluxei.mask.nxv1i32.nxv1i64.i64(<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
|
|
//
|
|
vint32mf2_t test_vluxei64_v_i32mf2_m(vbool64_t mask, vint32mf2_t maskedoff, const int32_t *base, vuint64m1_t bindex, size_t vl) {
|
|
return vluxei64(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei64_v_i32m1_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vluxei.mask.nxv2i32.nxv2i64.i64(<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]]
|
|
//
|
|
vint32m1_t test_vluxei64_v_i32m1_m(vbool32_t mask, vint32m1_t maskedoff, const int32_t *base, vuint64m2_t bindex, size_t vl) {
|
|
return vluxei64(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei64_v_i32m2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vluxei.mask.nxv4i32.nxv4i64.i64(<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]]
|
|
//
|
|
vint32m2_t test_vluxei64_v_i32m2_m(vbool16_t mask, vint32m2_t maskedoff, const int32_t *base, vuint64m4_t bindex, size_t vl) {
|
|
return vluxei64(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei64_v_i32m4_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vluxei.mask.nxv8i32.nxv8i64.i64(<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]]
|
|
//
|
|
vint32m4_t test_vluxei64_v_i32m4_m(vbool8_t mask, vint32m4_t maskedoff, const int32_t *base, vuint64m8_t bindex, size_t vl) {
|
|
return vluxei64(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_i64m1_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vluxei.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]]
|
|
//
|
|
vint64m1_t test_vluxei8_v_i64m1_m(vbool64_t mask, vint64m1_t maskedoff, const int64_t *base, vuint8mf8_t bindex, size_t vl) {
|
|
return vluxei8(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_i64m2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vluxei.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]]
|
|
//
|
|
vint64m2_t test_vluxei8_v_i64m2_m(vbool32_t mask, vint64m2_t maskedoff, const int64_t *base, vuint8mf4_t bindex, size_t vl) {
|
|
return vluxei8(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_i64m4_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vluxei.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]]
|
|
//
|
|
vint64m4_t test_vluxei8_v_i64m4_m(vbool16_t mask, vint64m4_t maskedoff, const int64_t *base, vuint8mf2_t bindex, size_t vl) {
|
|
return vluxei8(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_i64m8_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vluxei.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]]
|
|
//
|
|
vint64m8_t test_vluxei8_v_i64m8_m(vbool8_t mask, vint64m8_t maskedoff, const int64_t *base, vuint8m1_t bindex, size_t vl) {
|
|
return vluxei8(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_i64m1_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vluxei.mask.nxv1i64.nxv1i16.i64(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]]
|
|
//
|
|
vint64m1_t test_vluxei16_v_i64m1_m(vbool64_t mask, vint64m1_t maskedoff, const int64_t *base, vuint16mf4_t bindex, size_t vl) {
|
|
return vluxei16(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_i64m2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vluxei.mask.nxv2i64.nxv2i16.i64(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]]
|
|
//
|
|
vint64m2_t test_vluxei16_v_i64m2_m(vbool32_t mask, vint64m2_t maskedoff, const int64_t *base, vuint16mf2_t bindex, size_t vl) {
|
|
return vluxei16(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_i64m4_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vluxei.mask.nxv4i64.nxv4i16.i64(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]]
|
|
//
|
|
vint64m4_t test_vluxei16_v_i64m4_m(vbool16_t mask, vint64m4_t maskedoff, const int64_t *base, vuint16m1_t bindex, size_t vl) {
|
|
return vluxei16(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_i64m8_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vluxei.mask.nxv8i64.nxv8i16.i64(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]]
|
|
//
|
|
vint64m8_t test_vluxei16_v_i64m8_m(vbool8_t mask, vint64m8_t maskedoff, const int64_t *base, vuint16m2_t bindex, size_t vl) {
|
|
return vluxei16(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_i64m1_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vluxei.mask.nxv1i64.nxv1i32.i64(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]]
|
|
//
|
|
vint64m1_t test_vluxei32_v_i64m1_m(vbool64_t mask, vint64m1_t maskedoff, const int64_t *base, vuint32mf2_t bindex, size_t vl) {
|
|
return vluxei32(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_i64m2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vluxei.mask.nxv2i64.nxv2i32.i64(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]]
|
|
//
|
|
vint64m2_t test_vluxei32_v_i64m2_m(vbool32_t mask, vint64m2_t maskedoff, const int64_t *base, vuint32m1_t bindex, size_t vl) {
|
|
return vluxei32(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_i64m4_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vluxei.mask.nxv4i64.nxv4i32.i64(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]]
|
|
//
|
|
vint64m4_t test_vluxei32_v_i64m4_m(vbool16_t mask, vint64m4_t maskedoff, const int64_t *base, vuint32m2_t bindex, size_t vl) {
|
|
return vluxei32(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_i64m8_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vluxei.mask.nxv8i64.nxv8i32.i64(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]]
|
|
//
|
|
vint64m8_t test_vluxei32_v_i64m8_m(vbool8_t mask, vint64m8_t maskedoff, const int64_t *base, vuint32m4_t bindex, size_t vl) {
|
|
return vluxei32(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei64_v_i64m1_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vluxei.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]]
|
|
//
|
|
vint64m1_t test_vluxei64_v_i64m1_m(vbool64_t mask, vint64m1_t maskedoff, const int64_t *base, vuint64m1_t bindex, size_t vl) {
|
|
return vluxei64(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei64_v_i64m2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vluxei.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]]
|
|
//
|
|
vint64m2_t test_vluxei64_v_i64m2_m(vbool32_t mask, vint64m2_t maskedoff, const int64_t *base, vuint64m2_t bindex, size_t vl) {
|
|
return vluxei64(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei64_v_i64m4_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vluxei.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]]
|
|
//
|
|
vint64m4_t test_vluxei64_v_i64m4_m(vbool16_t mask, vint64m4_t maskedoff, const int64_t *base, vuint64m4_t bindex, size_t vl) {
|
|
return vluxei64(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei64_v_i64m8_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vluxei.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]]
|
|
//
|
|
vint64m8_t test_vluxei64_v_i64m8_m(vbool8_t mask, vint64m8_t maskedoff, const int64_t *base, vuint64m8_t bindex, size_t vl) {
|
|
return vluxei64(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_u8mf8_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vluxei.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
|
|
//
|
|
vuint8mf8_t test_vluxei8_v_u8mf8_m(vbool64_t mask, vuint8mf8_t maskedoff, const uint8_t *base, vuint8mf8_t bindex, size_t vl) {
|
|
return vluxei8(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_u8mf4_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vluxei.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]]
|
|
//
|
|
vuint8mf4_t test_vluxei8_v_u8mf4_m(vbool32_t mask, vuint8mf4_t maskedoff, const uint8_t *base, vuint8mf4_t bindex, size_t vl) {
|
|
return vluxei8(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_u8mf2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vluxei.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]]
|
|
//
|
|
vuint8mf2_t test_vluxei8_v_u8mf2_m(vbool16_t mask, vuint8mf2_t maskedoff, const uint8_t *base, vuint8mf2_t bindex, size_t vl) {
|
|
return vluxei8(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_u8m1_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vluxei.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]]
|
|
//
|
|
vuint8m1_t test_vluxei8_v_u8m1_m(vbool8_t mask, vuint8m1_t maskedoff, const uint8_t *base, vuint8m1_t bindex, size_t vl) {
|
|
return vluxei8(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_u8m2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vluxei.mask.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x i8>* [[TMP0]], <vscale x 16 x i8> [[BINDEX:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP1]]
|
|
//
|
|
vuint8m2_t test_vluxei8_v_u8m2_m(vbool4_t mask, vuint8m2_t maskedoff, const uint8_t *base, vuint8m2_t bindex, size_t vl) {
|
|
return vluxei8(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_u8m4_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vluxei.mask.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x i8>* [[TMP0]], <vscale x 32 x i8> [[BINDEX:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP1]]
|
|
//
|
|
vuint8m4_t test_vluxei8_v_u8m4_m(vbool2_t mask, vuint8m4_t maskedoff, const uint8_t *base, vuint8m4_t bindex, size_t vl) {
|
|
return vluxei8(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_u8m8_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 64 x i8> @llvm.riscv.vluxei.mask.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> [[MASKEDOFF:%.*]], <vscale x 64 x i8>* [[TMP0]], <vscale x 64 x i8> [[BINDEX:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP1]]
|
|
//
|
|
vuint8m8_t test_vluxei8_v_u8m8_m(vbool1_t mask, vuint8m8_t maskedoff, const uint8_t *base, vuint8m8_t bindex, size_t vl) {
|
|
return vluxei8(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_u8mf8_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vluxei.mask.nxv1i8.nxv1i16.i64(<vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
|
|
//
|
|
vuint8mf8_t test_vluxei16_v_u8mf8_m(vbool64_t mask, vuint8mf8_t maskedoff, const uint8_t *base, vuint16mf4_t bindex, size_t vl) {
|
|
return vluxei16(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_u8mf4_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vluxei.mask.nxv2i8.nxv2i16.i64(<vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]]
|
|
//
|
|
vuint8mf4_t test_vluxei16_v_u8mf4_m(vbool32_t mask, vuint8mf4_t maskedoff, const uint8_t *base, vuint16mf2_t bindex, size_t vl) {
|
|
return vluxei16(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_u8mf2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vluxei.mask.nxv4i8.nxv4i16.i64(<vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]]
|
|
//
|
|
vuint8mf2_t test_vluxei16_v_u8mf2_m(vbool16_t mask, vuint8mf2_t maskedoff, const uint8_t *base, vuint16m1_t bindex, size_t vl) {
|
|
return vluxei16(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_u8m1_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vluxei.mask.nxv8i8.nxv8i16.i64(<vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]]
|
|
//
|
|
vuint8m1_t test_vluxei16_v_u8m1_m(vbool8_t mask, vuint8m1_t maskedoff, const uint8_t *base, vuint16m2_t bindex, size_t vl) {
|
|
return vluxei16(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_u8m2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vluxei.mask.nxv16i8.nxv16i16.i64(<vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x i8>* [[TMP0]], <vscale x 16 x i16> [[BINDEX:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP1]]
|
|
//
|
|
vuint8m2_t test_vluxei16_v_u8m2_m(vbool4_t mask, vuint8m2_t maskedoff, const uint8_t *base, vuint16m4_t bindex, size_t vl) {
|
|
return vluxei16(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_u8m4_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i8> @llvm.riscv.vluxei.mask.nxv32i8.nxv32i16.i64(<vscale x 32 x i8> [[MASKEDOFF:%.*]], <vscale x 32 x i8>* [[TMP0]], <vscale x 32 x i16> [[BINDEX:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP1]]
|
|
//
|
|
vuint8m4_t test_vluxei16_v_u8m4_m(vbool2_t mask, vuint8m4_t maskedoff, const uint8_t *base, vuint16m8_t bindex, size_t vl) {
|
|
return vluxei16(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_u8mf8_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vluxei.mask.nxv1i8.nxv1i32.i64(<vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
|
|
//
|
|
vuint8mf8_t test_vluxei32_v_u8mf8_m(vbool64_t mask, vuint8mf8_t maskedoff, const uint8_t *base, vuint32mf2_t bindex, size_t vl) {
|
|
return vluxei32(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_u8mf4_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vluxei.mask.nxv2i8.nxv2i32.i64(<vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]]
|
|
//
|
|
vuint8mf4_t test_vluxei32_v_u8mf4_m(vbool32_t mask, vuint8mf4_t maskedoff, const uint8_t *base, vuint32m1_t bindex, size_t vl) {
|
|
return vluxei32(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_u8mf2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vluxei.mask.nxv4i8.nxv4i32.i64(<vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]]
|
|
//
|
|
vuint8mf2_t test_vluxei32_v_u8mf2_m(vbool16_t mask, vuint8mf2_t maskedoff, const uint8_t *base, vuint32m2_t bindex, size_t vl) {
|
|
return vluxei32(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_u8m1_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vluxei.mask.nxv8i8.nxv8i32.i64(<vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]]
|
|
//
|
|
vuint8m1_t test_vluxei32_v_u8m1_m(vbool8_t mask, vuint8m1_t maskedoff, const uint8_t *base, vuint32m4_t bindex, size_t vl) {
|
|
return vluxei32(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_u8m2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i8> @llvm.riscv.vluxei.mask.nxv16i8.nxv16i32.i64(<vscale x 16 x i8> [[MASKEDOFF:%.*]], <vscale x 16 x i8>* [[TMP0]], <vscale x 16 x i32> [[BINDEX:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP1]]
|
|
//
|
|
vuint8m2_t test_vluxei32_v_u8m2_m(vbool4_t mask, vuint8m2_t maskedoff, const uint8_t *base, vuint32m8_t bindex, size_t vl) {
|
|
return vluxei32(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei64_v_u8mf8_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vluxei.mask.nxv1i8.nxv1i64.i64(<vscale x 1 x i8> [[MASKEDOFF:%.*]], <vscale x 1 x i8>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP1]]
|
|
//
|
|
vuint8mf8_t test_vluxei64_v_u8mf8_m(vbool64_t mask, vuint8mf8_t maskedoff, const uint8_t *base, vuint64m1_t bindex, size_t vl) {
|
|
return vluxei64(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei64_v_u8mf4_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vluxei.mask.nxv2i8.nxv2i64.i64(<vscale x 2 x i8> [[MASKEDOFF:%.*]], <vscale x 2 x i8>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP1]]
|
|
//
|
|
vuint8mf4_t test_vluxei64_v_u8mf4_m(vbool32_t mask, vuint8mf4_t maskedoff, const uint8_t *base, vuint64m2_t bindex, size_t vl) {
|
|
return vluxei64(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei64_v_u8mf2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vluxei.mask.nxv4i8.nxv4i64.i64(<vscale x 4 x i8> [[MASKEDOFF:%.*]], <vscale x 4 x i8>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP1]]
|
|
//
|
|
vuint8mf2_t test_vluxei64_v_u8mf2_m(vbool16_t mask, vuint8mf2_t maskedoff, const uint8_t *base, vuint64m4_t bindex, size_t vl) {
|
|
return vluxei64(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei64_v_u8m1_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vluxei.mask.nxv8i8.nxv8i64.i64(<vscale x 8 x i8> [[MASKEDOFF:%.*]], <vscale x 8 x i8>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP1]]
|
|
//
|
|
vuint8m1_t test_vluxei64_v_u8m1_m(vbool8_t mask, vuint8m1_t maskedoff, const uint8_t *base, vuint64m8_t bindex, size_t vl) {
|
|
return vluxei64(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_u16mf4_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vluxei.mask.nxv1i16.nxv1i8.i64(<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]]
|
|
//
|
|
vuint16mf4_t test_vluxei8_v_u16mf4_m(vbool64_t mask, vuint16mf4_t maskedoff, const uint16_t *base, vuint8mf8_t bindex, size_t vl) {
|
|
return vluxei8(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_u16mf2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vluxei.mask.nxv2i16.nxv2i8.i64(<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]]
|
|
//
|
|
vuint16mf2_t test_vluxei8_v_u16mf2_m(vbool32_t mask, vuint16mf2_t maskedoff, const uint16_t *base, vuint8mf4_t bindex, size_t vl) {
|
|
return vluxei8(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_u16m1_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vluxei.mask.nxv4i16.nxv4i8.i64(<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]]
|
|
//
|
|
vuint16m1_t test_vluxei8_v_u16m1_m(vbool16_t mask, vuint16m1_t maskedoff, const uint16_t *base, vuint8mf2_t bindex, size_t vl) {
|
|
return vluxei8(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_u16m2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vluxei.mask.nxv8i16.nxv8i8.i64(<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]]
|
|
//
|
|
vuint16m2_t test_vluxei8_v_u16m2_m(vbool8_t mask, vuint16m2_t maskedoff, const uint16_t *base, vuint8m1_t bindex, size_t vl) {
|
|
return vluxei8(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_u16m4_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vluxei.mask.nxv16i16.nxv16i8.i64(<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16>* [[TMP0]], <vscale x 16 x i8> [[BINDEX:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP1]]
|
|
//
|
|
vuint16m4_t test_vluxei8_v_u16m4_m(vbool4_t mask, vuint16m4_t maskedoff, const uint16_t *base, vuint8m2_t bindex, size_t vl) {
|
|
return vluxei8(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_u16m8_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vluxei.mask.nxv32i16.nxv32i8.i64(<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i16>* [[TMP0]], <vscale x 32 x i8> [[BINDEX:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP1]]
|
|
//
|
|
vuint16m8_t test_vluxei8_v_u16m8_m(vbool2_t mask, vuint16m8_t maskedoff, const uint16_t *base, vuint8m4_t bindex, size_t vl) {
|
|
return vluxei8(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_u16mf4_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vluxei.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]]
|
|
//
|
|
vuint16mf4_t test_vluxei16_v_u16mf4_m(vbool64_t mask, vuint16mf4_t maskedoff, const uint16_t *base, vuint16mf4_t bindex, size_t vl) {
|
|
return vluxei16(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_u16mf2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vluxei.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]]
|
|
//
|
|
vuint16mf2_t test_vluxei16_v_u16mf2_m(vbool32_t mask, vuint16mf2_t maskedoff, const uint16_t *base, vuint16mf2_t bindex, size_t vl) {
|
|
return vluxei16(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_u16m1_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vluxei.mask.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]]
|
|
//
|
|
vuint16m1_t test_vluxei16_v_u16m1_m(vbool16_t mask, vuint16m1_t maskedoff, const uint16_t *base, vuint16m1_t bindex, size_t vl) {
|
|
return vluxei16(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_u16m2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vluxei.mask.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]]
|
|
//
|
|
vuint16m2_t test_vluxei16_v_u16m2_m(vbool8_t mask, vuint16m2_t maskedoff, const uint16_t *base, vuint16m2_t bindex, size_t vl) {
|
|
return vluxei16(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_u16m4_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vluxei.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16>* [[TMP0]], <vscale x 16 x i16> [[BINDEX:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP1]]
|
|
//
|
|
vuint16m4_t test_vluxei16_v_u16m4_m(vbool4_t mask, vuint16m4_t maskedoff, const uint16_t *base, vuint16m4_t bindex, size_t vl) {
|
|
return vluxei16(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_u16m8_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i16> @llvm.riscv.vluxei.mask.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> [[MASKEDOFF:%.*]], <vscale x 32 x i16>* [[TMP0]], <vscale x 32 x i16> [[BINDEX:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 32 x i16> [[TMP1]]
|
|
//
|
|
vuint16m8_t test_vluxei16_v_u16m8_m(vbool2_t mask, vuint16m8_t maskedoff, const uint16_t *base, vuint16m8_t bindex, size_t vl) {
|
|
return vluxei16(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_u16mf4_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vluxei.mask.nxv1i16.nxv1i32.i64(<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]]
|
|
//
|
|
vuint16mf4_t test_vluxei32_v_u16mf4_m(vbool64_t mask, vuint16mf4_t maskedoff, const uint16_t *base, vuint32mf2_t bindex, size_t vl) {
|
|
return vluxei32(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_u16mf2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vluxei.mask.nxv2i16.nxv2i32.i64(<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]]
|
|
//
|
|
vuint16mf2_t test_vluxei32_v_u16mf2_m(vbool32_t mask, vuint16mf2_t maskedoff, const uint16_t *base, vuint32m1_t bindex, size_t vl) {
|
|
return vluxei32(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_u16m1_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vluxei.mask.nxv4i16.nxv4i32.i64(<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]]
|
|
//
|
|
vuint16m1_t test_vluxei32_v_u16m1_m(vbool16_t mask, vuint16m1_t maskedoff, const uint16_t *base, vuint32m2_t bindex, size_t vl) {
|
|
return vluxei32(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_u16m2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vluxei.mask.nxv8i16.nxv8i32.i64(<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]]
|
|
//
|
|
vuint16m2_t test_vluxei32_v_u16m2_m(vbool8_t mask, vuint16m2_t maskedoff, const uint16_t *base, vuint32m4_t bindex, size_t vl) {
|
|
return vluxei32(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_u16m4_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i16> @llvm.riscv.vluxei.mask.nxv16i16.nxv16i32.i64(<vscale x 16 x i16> [[MASKEDOFF:%.*]], <vscale x 16 x i16>* [[TMP0]], <vscale x 16 x i32> [[BINDEX:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 16 x i16> [[TMP1]]
|
|
//
|
|
vuint16m4_t test_vluxei32_v_u16m4_m(vbool4_t mask, vuint16m4_t maskedoff, const uint16_t *base, vuint32m8_t bindex, size_t vl) {
|
|
return vluxei32(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei64_v_u16mf4_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i16> @llvm.riscv.vluxei.mask.nxv1i16.nxv1i64.i64(<vscale x 1 x i16> [[MASKEDOFF:%.*]], <vscale x 1 x i16>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i16> [[TMP1]]
|
|
//
|
|
vuint16mf4_t test_vluxei64_v_u16mf4_m(vbool64_t mask, vuint16mf4_t maskedoff, const uint16_t *base, vuint64m1_t bindex, size_t vl) {
|
|
return vluxei64(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei64_v_u16mf2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i16> @llvm.riscv.vluxei.mask.nxv2i16.nxv2i64.i64(<vscale x 2 x i16> [[MASKEDOFF:%.*]], <vscale x 2 x i16>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i16> [[TMP1]]
|
|
//
|
|
vuint16mf2_t test_vluxei64_v_u16mf2_m(vbool32_t mask, vuint16mf2_t maskedoff, const uint16_t *base, vuint64m2_t bindex, size_t vl) {
|
|
return vluxei64(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei64_v_u16m1_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vluxei.mask.nxv4i16.nxv4i64.i64(<vscale x 4 x i16> [[MASKEDOFF:%.*]], <vscale x 4 x i16>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i16> [[TMP1]]
|
|
//
|
|
vuint16m1_t test_vluxei64_v_u16m1_m(vbool16_t mask, vuint16m1_t maskedoff, const uint16_t *base, vuint64m4_t bindex, size_t vl) {
|
|
return vluxei64(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei64_v_u16m2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i16> @llvm.riscv.vluxei.mask.nxv8i16.nxv8i64.i64(<vscale x 8 x i16> [[MASKEDOFF:%.*]], <vscale x 8 x i16>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i16> [[TMP1]]
|
|
//
|
|
vuint16m2_t test_vluxei64_v_u16m2_m(vbool8_t mask, vuint16m2_t maskedoff, const uint16_t *base, vuint64m8_t bindex, size_t vl) {
|
|
return vluxei64(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_u32mf2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vluxei.mask.nxv1i32.nxv1i8.i64(<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
|
|
//
|
|
vuint32mf2_t test_vluxei8_v_u32mf2_m(vbool64_t mask, vuint32mf2_t maskedoff, const uint32_t *base, vuint8mf8_t bindex, size_t vl) {
|
|
return vluxei8(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_u32m1_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vluxei.mask.nxv2i32.nxv2i8.i64(<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]]
|
|
//
|
|
vuint32m1_t test_vluxei8_v_u32m1_m(vbool32_t mask, vuint32m1_t maskedoff, const uint32_t *base, vuint8mf4_t bindex, size_t vl) {
|
|
return vluxei8(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_u32m2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vluxei.mask.nxv4i32.nxv4i8.i64(<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]]
|
|
//
|
|
vuint32m2_t test_vluxei8_v_u32m2_m(vbool16_t mask, vuint32m2_t maskedoff, const uint32_t *base, vuint8mf2_t bindex, size_t vl) {
|
|
return vluxei8(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_u32m4_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vluxei.mask.nxv8i32.nxv8i8.i64(<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]]
|
|
//
|
|
vuint32m4_t test_vluxei8_v_u32m4_m(vbool8_t mask, vuint32m4_t maskedoff, const uint32_t *base, vuint8m1_t bindex, size_t vl) {
|
|
return vluxei8(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_u32m8_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vluxei.mask.nxv16i32.nxv16i8.i64(<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32>* [[TMP0]], <vscale x 16 x i8> [[BINDEX:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP1]]
|
|
//
|
|
vuint32m8_t test_vluxei8_v_u32m8_m(vbool4_t mask, vuint32m8_t maskedoff, const uint32_t *base, vuint8m2_t bindex, size_t vl) {
|
|
return vluxei8(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_u32mf2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vluxei.mask.nxv1i32.nxv1i16.i64(<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
|
|
//
|
|
vuint32mf2_t test_vluxei16_v_u32mf2_m(vbool64_t mask, vuint32mf2_t maskedoff, const uint32_t *base, vuint16mf4_t bindex, size_t vl) {
|
|
return vluxei16(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_u32m1_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vluxei.mask.nxv2i32.nxv2i16.i64(<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]]
|
|
//
|
|
vuint32m1_t test_vluxei16_v_u32m1_m(vbool32_t mask, vuint32m1_t maskedoff, const uint32_t *base, vuint16mf2_t bindex, size_t vl) {
|
|
return vluxei16(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_u32m2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vluxei.mask.nxv4i32.nxv4i16.i64(<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]]
|
|
//
|
|
vuint32m2_t test_vluxei16_v_u32m2_m(vbool16_t mask, vuint32m2_t maskedoff, const uint32_t *base, vuint16m1_t bindex, size_t vl) {
|
|
return vluxei16(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_u32m4_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vluxei.mask.nxv8i32.nxv8i16.i64(<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]]
|
|
//
|
|
vuint32m4_t test_vluxei16_v_u32m4_m(vbool8_t mask, vuint32m4_t maskedoff, const uint32_t *base, vuint16m2_t bindex, size_t vl) {
|
|
return vluxei16(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_u32m8_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vluxei.mask.nxv16i32.nxv16i16.i64(<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32>* [[TMP0]], <vscale x 16 x i16> [[BINDEX:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP1]]
|
|
//
|
|
vuint32m8_t test_vluxei16_v_u32m8_m(vbool4_t mask, vuint32m8_t maskedoff, const uint32_t *base, vuint16m4_t bindex, size_t vl) {
|
|
return vluxei16(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_u32mf2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vluxei.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
|
|
//
|
|
vuint32mf2_t test_vluxei32_v_u32mf2_m(vbool64_t mask, vuint32mf2_t maskedoff, const uint32_t *base, vuint32mf2_t bindex, size_t vl) {
|
|
return vluxei32(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_u32m1_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vluxei.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]]
|
|
//
|
|
vuint32m1_t test_vluxei32_v_u32m1_m(vbool32_t mask, vuint32m1_t maskedoff, const uint32_t *base, vuint32m1_t bindex, size_t vl) {
|
|
return vluxei32(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_u32m2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vluxei.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]]
|
|
//
|
|
vuint32m2_t test_vluxei32_v_u32m2_m(vbool16_t mask, vuint32m2_t maskedoff, const uint32_t *base, vuint32m2_t bindex, size_t vl) {
|
|
return vluxei32(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_u32m4_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vluxei.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]]
|
|
//
|
|
vuint32m4_t test_vluxei32_v_u32m4_m(vbool8_t mask, vuint32m4_t maskedoff, const uint32_t *base, vuint32m4_t bindex, size_t vl) {
|
|
return vluxei32(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_u32m8_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vluxei.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[MASKEDOFF:%.*]], <vscale x 16 x i32>* [[TMP0]], <vscale x 16 x i32> [[BINDEX:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP1]]
|
|
//
|
|
vuint32m8_t test_vluxei32_v_u32m8_m(vbool4_t mask, vuint32m8_t maskedoff, const uint32_t *base, vuint32m8_t bindex, size_t vl) {
|
|
return vluxei32(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei64_v_u32mf2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vluxei.mask.nxv1i32.nxv1i64.i64(<vscale x 1 x i32> [[MASKEDOFF:%.*]], <vscale x 1 x i32>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP1]]
|
|
//
|
|
vuint32mf2_t test_vluxei64_v_u32mf2_m(vbool64_t mask, vuint32mf2_t maskedoff, const uint32_t *base, vuint64m1_t bindex, size_t vl) {
|
|
return vluxei64(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei64_v_u32m1_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vluxei.mask.nxv2i32.nxv2i64.i64(<vscale x 2 x i32> [[MASKEDOFF:%.*]], <vscale x 2 x i32>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP1]]
|
|
//
|
|
vuint32m1_t test_vluxei64_v_u32m1_m(vbool32_t mask, vuint32m1_t maskedoff, const uint32_t *base, vuint64m2_t bindex, size_t vl) {
|
|
return vluxei64(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei64_v_u32m2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vluxei.mask.nxv4i32.nxv4i64.i64(<vscale x 4 x i32> [[MASKEDOFF:%.*]], <vscale x 4 x i32>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP1]]
|
|
//
|
|
vuint32m2_t test_vluxei64_v_u32m2_m(vbool16_t mask, vuint32m2_t maskedoff, const uint32_t *base, vuint64m4_t bindex, size_t vl) {
|
|
return vluxei64(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei64_v_u32m4_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vluxei.mask.nxv8i32.nxv8i64.i64(<vscale x 8 x i32> [[MASKEDOFF:%.*]], <vscale x 8 x i32>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP1]]
|
|
//
|
|
vuint32m4_t test_vluxei64_v_u32m4_m(vbool8_t mask, vuint32m4_t maskedoff, const uint32_t *base, vuint64m8_t bindex, size_t vl) {
|
|
return vluxei64(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_u64m1_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vluxei.mask.nxv1i64.nxv1i8.i64(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]]
|
|
//
|
|
vuint64m1_t test_vluxei8_v_u64m1_m(vbool64_t mask, vuint64m1_t maskedoff, const uint64_t *base, vuint8mf8_t bindex, size_t vl) {
|
|
return vluxei8(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_u64m2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vluxei.mask.nxv2i64.nxv2i8.i64(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]]
|
|
//
|
|
vuint64m2_t test_vluxei8_v_u64m2_m(vbool32_t mask, vuint64m2_t maskedoff, const uint64_t *base, vuint8mf4_t bindex, size_t vl) {
|
|
return vluxei8(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_u64m4_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vluxei.mask.nxv4i64.nxv4i8.i64(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]]
|
|
//
|
|
vuint64m4_t test_vluxei8_v_u64m4_m(vbool16_t mask, vuint64m4_t maskedoff, const uint64_t *base, vuint8mf2_t bindex, size_t vl) {
|
|
return vluxei8(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_u64m8_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vluxei.mask.nxv8i64.nxv8i8.i64(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]]
|
|
//
|
|
vuint64m8_t test_vluxei8_v_u64m8_m(vbool8_t mask, vuint64m8_t maskedoff, const uint64_t *base, vuint8m1_t bindex, size_t vl) {
|
|
return vluxei8(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_u64m1_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vluxei.mask.nxv1i64.nxv1i16.i64(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]]
|
|
//
|
|
vuint64m1_t test_vluxei16_v_u64m1_m(vbool64_t mask, vuint64m1_t maskedoff, const uint64_t *base, vuint16mf4_t bindex, size_t vl) {
|
|
return vluxei16(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_u64m2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vluxei.mask.nxv2i64.nxv2i16.i64(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]]
|
|
//
|
|
vuint64m2_t test_vluxei16_v_u64m2_m(vbool32_t mask, vuint64m2_t maskedoff, const uint64_t *base, vuint16mf2_t bindex, size_t vl) {
|
|
return vluxei16(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_u64m4_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vluxei.mask.nxv4i64.nxv4i16.i64(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]]
|
|
//
|
|
vuint64m4_t test_vluxei16_v_u64m4_m(vbool16_t mask, vuint64m4_t maskedoff, const uint64_t *base, vuint16m1_t bindex, size_t vl) {
|
|
return vluxei16(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_u64m8_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vluxei.mask.nxv8i64.nxv8i16.i64(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]]
|
|
//
|
|
vuint64m8_t test_vluxei16_v_u64m8_m(vbool8_t mask, vuint64m8_t maskedoff, const uint64_t *base, vuint16m2_t bindex, size_t vl) {
|
|
return vluxei16(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_u64m1_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vluxei.mask.nxv1i64.nxv1i32.i64(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]]
|
|
//
|
|
vuint64m1_t test_vluxei32_v_u64m1_m(vbool64_t mask, vuint64m1_t maskedoff, const uint64_t *base, vuint32mf2_t bindex, size_t vl) {
|
|
return vluxei32(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_u64m2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vluxei.mask.nxv2i64.nxv2i32.i64(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]]
|
|
//
|
|
vuint64m2_t test_vluxei32_v_u64m2_m(vbool32_t mask, vuint64m2_t maskedoff, const uint64_t *base, vuint32m1_t bindex, size_t vl) {
|
|
return vluxei32(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_u64m4_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vluxei.mask.nxv4i64.nxv4i32.i64(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]]
|
|
//
|
|
vuint64m4_t test_vluxei32_v_u64m4_m(vbool16_t mask, vuint64m4_t maskedoff, const uint64_t *base, vuint32m2_t bindex, size_t vl) {
|
|
return vluxei32(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_u64m8_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vluxei.mask.nxv8i64.nxv8i32.i64(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]]
|
|
//
|
|
vuint64m8_t test_vluxei32_v_u64m8_m(vbool8_t mask, vuint64m8_t maskedoff, const uint64_t *base, vuint32m4_t bindex, size_t vl) {
|
|
return vluxei32(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei64_v_u64m1_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vluxei.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> [[MASKEDOFF:%.*]], <vscale x 1 x i64>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP1]]
|
|
//
|
|
vuint64m1_t test_vluxei64_v_u64m1_m(vbool64_t mask, vuint64m1_t maskedoff, const uint64_t *base, vuint64m1_t bindex, size_t vl) {
|
|
return vluxei64(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei64_v_u64m2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i64> @llvm.riscv.vluxei.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> [[MASKEDOFF:%.*]], <vscale x 2 x i64>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x i64> [[TMP1]]
|
|
//
|
|
vuint64m2_t test_vluxei64_v_u64m2_m(vbool32_t mask, vuint64m2_t maskedoff, const uint64_t *base, vuint64m2_t bindex, size_t vl) {
|
|
return vluxei64(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei64_v_u64m4_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i64> @llvm.riscv.vluxei.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> [[MASKEDOFF:%.*]], <vscale x 4 x i64>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x i64> [[TMP1]]
|
|
//
|
|
vuint64m4_t test_vluxei64_v_u64m4_m(vbool16_t mask, vuint64m4_t maskedoff, const uint64_t *base, vuint64m4_t bindex, size_t vl) {
|
|
return vluxei64(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei64_v_u64m8_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i64> @llvm.riscv.vluxei.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> [[MASKEDOFF:%.*]], <vscale x 8 x i64>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x i64> [[TMP1]]
|
|
//
|
|
vuint64m8_t test_vluxei64_v_u64m8_m(vbool8_t mask, vuint64m8_t maskedoff, const uint64_t *base, vuint64m8_t bindex, size_t vl) {
|
|
return vluxei64(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_f32mf2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vluxei.mask.nxv1f32.nxv1i8.i64(<vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x float>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]]
|
|
//
|
|
vfloat32mf2_t test_vluxei8_v_f32mf2_m(vbool64_t mask, vfloat32mf2_t maskedoff, const float *base, vuint8mf8_t bindex, size_t vl) {
|
|
return vluxei8(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_f32m1_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 2 x float>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x float> @llvm.riscv.vluxei.mask.nxv2f32.nxv2i8.i64(<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x float>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP1]]
|
|
//
|
|
vfloat32m1_t test_vluxei8_v_f32m1_m(vbool32_t mask, vfloat32m1_t maskedoff, const float *base, vuint8mf4_t bindex, size_t vl) {
|
|
return vluxei8(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_f32m2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 4 x float>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x float> @llvm.riscv.vluxei.mask.nxv4f32.nxv4i8.i64(<vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x float>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP1]]
|
|
//
|
|
vfloat32m2_t test_vluxei8_v_f32m2_m(vbool16_t mask, vfloat32m2_t maskedoff, const float *base, vuint8mf2_t bindex, size_t vl) {
|
|
return vluxei8(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_f32m4_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 8 x float>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x float> @llvm.riscv.vluxei.mask.nxv8f32.nxv8i8.i64(<vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x float>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP1]]
|
|
//
|
|
vfloat32m4_t test_vluxei8_v_f32m4_m(vbool8_t mask, vfloat32m4_t maskedoff, const float *base, vuint8m1_t bindex, size_t vl) {
|
|
return vluxei8(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_f32m8_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 16 x float>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x float> @llvm.riscv.vluxei.mask.nxv16f32.nxv16i8.i64(<vscale x 16 x float> [[MASKEDOFF:%.*]], <vscale x 16 x float>* [[TMP0]], <vscale x 16 x i8> [[BINDEX:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP1]]
|
|
//
|
|
vfloat32m8_t test_vluxei8_v_f32m8_m(vbool4_t mask, vfloat32m8_t maskedoff, const float *base, vuint8m2_t bindex, size_t vl) {
|
|
return vluxei8(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_f32mf2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vluxei.mask.nxv1f32.nxv1i16.i64(<vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x float>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]]
|
|
//
|
|
vfloat32mf2_t test_vluxei16_v_f32mf2_m(vbool64_t mask, vfloat32mf2_t maskedoff, const float *base, vuint16mf4_t bindex, size_t vl) {
|
|
return vluxei16(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_f32m1_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 2 x float>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x float> @llvm.riscv.vluxei.mask.nxv2f32.nxv2i16.i64(<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x float>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP1]]
|
|
//
|
|
vfloat32m1_t test_vluxei16_v_f32m1_m(vbool32_t mask, vfloat32m1_t maskedoff, const float *base, vuint16mf2_t bindex, size_t vl) {
|
|
return vluxei16(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_f32m2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 4 x float>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x float> @llvm.riscv.vluxei.mask.nxv4f32.nxv4i16.i64(<vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x float>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP1]]
|
|
//
|
|
vfloat32m2_t test_vluxei16_v_f32m2_m(vbool16_t mask, vfloat32m2_t maskedoff, const float *base, vuint16m1_t bindex, size_t vl) {
|
|
return vluxei16(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_f32m4_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 8 x float>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x float> @llvm.riscv.vluxei.mask.nxv8f32.nxv8i16.i64(<vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x float>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP1]]
|
|
//
|
|
vfloat32m4_t test_vluxei16_v_f32m4_m(vbool8_t mask, vfloat32m4_t maskedoff, const float *base, vuint16m2_t bindex, size_t vl) {
|
|
return vluxei16(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_f32m8_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 16 x float>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x float> @llvm.riscv.vluxei.mask.nxv16f32.nxv16i16.i64(<vscale x 16 x float> [[MASKEDOFF:%.*]], <vscale x 16 x float>* [[TMP0]], <vscale x 16 x i16> [[BINDEX:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP1]]
|
|
//
|
|
vfloat32m8_t test_vluxei16_v_f32m8_m(vbool4_t mask, vfloat32m8_t maskedoff, const float *base, vuint16m4_t bindex, size_t vl) {
|
|
return vluxei16(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_f32mf2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vluxei.mask.nxv1f32.nxv1i32.i64(<vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x float>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]]
|
|
//
|
|
vfloat32mf2_t test_vluxei32_v_f32mf2_m(vbool64_t mask, vfloat32mf2_t maskedoff, const float *base, vuint32mf2_t bindex, size_t vl) {
|
|
return vluxei32(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_f32m1_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 2 x float>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x float> @llvm.riscv.vluxei.mask.nxv2f32.nxv2i32.i64(<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x float>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP1]]
|
|
//
|
|
vfloat32m1_t test_vluxei32_v_f32m1_m(vbool32_t mask, vfloat32m1_t maskedoff, const float *base, vuint32m1_t bindex, size_t vl) {
|
|
return vluxei32(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_f32m2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 4 x float>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x float> @llvm.riscv.vluxei.mask.nxv4f32.nxv4i32.i64(<vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x float>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP1]]
|
|
//
|
|
vfloat32m2_t test_vluxei32_v_f32m2_m(vbool16_t mask, vfloat32m2_t maskedoff, const float *base, vuint32m2_t bindex, size_t vl) {
|
|
return vluxei32(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_f32m4_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 8 x float>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x float> @llvm.riscv.vluxei.mask.nxv8f32.nxv8i32.i64(<vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x float>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP1]]
|
|
//
|
|
vfloat32m4_t test_vluxei32_v_f32m4_m(vbool8_t mask, vfloat32m4_t maskedoff, const float *base, vuint32m4_t bindex, size_t vl) {
|
|
return vluxei32(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_f32m8_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 16 x float>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x float> @llvm.riscv.vluxei.mask.nxv16f32.nxv16i32.i64(<vscale x 16 x float> [[MASKEDOFF:%.*]], <vscale x 16 x float>* [[TMP0]], <vscale x 16 x i32> [[BINDEX:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP1]]
|
|
//
|
|
vfloat32m8_t test_vluxei32_v_f32m8_m(vbool4_t mask, vfloat32m8_t maskedoff, const float *base, vuint32m8_t bindex, size_t vl) {
|
|
return vluxei32(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei64_v_f32mf2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x float> @llvm.riscv.vluxei.mask.nxv1f32.nxv1i64.i64(<vscale x 1 x float> [[MASKEDOFF:%.*]], <vscale x 1 x float>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP1]]
|
|
//
|
|
vfloat32mf2_t test_vluxei64_v_f32mf2_m(vbool64_t mask, vfloat32mf2_t maskedoff, const float *base, vuint64m1_t bindex, size_t vl) {
|
|
return vluxei64(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei64_v_f32m1_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 2 x float>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x float> @llvm.riscv.vluxei.mask.nxv2f32.nxv2i64.i64(<vscale x 2 x float> [[MASKEDOFF:%.*]], <vscale x 2 x float>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP1]]
|
|
//
|
|
vfloat32m1_t test_vluxei64_v_f32m1_m(vbool32_t mask, vfloat32m1_t maskedoff, const float *base, vuint64m2_t bindex, size_t vl) {
|
|
return vluxei64(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei64_v_f32m2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 4 x float>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x float> @llvm.riscv.vluxei.mask.nxv4f32.nxv4i64.i64(<vscale x 4 x float> [[MASKEDOFF:%.*]], <vscale x 4 x float>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP1]]
|
|
//
|
|
vfloat32m2_t test_vluxei64_v_f32m2_m(vbool16_t mask, vfloat32m2_t maskedoff, const float *base, vuint64m4_t bindex, size_t vl) {
|
|
return vluxei64(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei64_v_f32m4_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 8 x float>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x float> @llvm.riscv.vluxei.mask.nxv8f32.nxv8i64.i64(<vscale x 8 x float> [[MASKEDOFF:%.*]], <vscale x 8 x float>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP1]]
|
|
//
|
|
vfloat32m4_t test_vluxei64_v_f32m4_m(vbool8_t mask, vfloat32m4_t maskedoff, const float *base, vuint64m8_t bindex, size_t vl) {
|
|
return vluxei64(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_f64m1_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 1 x double>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x double> @llvm.riscv.vluxei.mask.nxv1f64.nxv1i8.i64(<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x double>* [[TMP0]], <vscale x 1 x i8> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP1]]
|
|
//
|
|
vfloat64m1_t test_vluxei8_v_f64m1_m(vbool64_t mask, vfloat64m1_t maskedoff, const double *base, vuint8mf8_t bindex, size_t vl) {
|
|
return vluxei8(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_f64m2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 2 x double>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x double> @llvm.riscv.vluxei.mask.nxv2f64.nxv2i8.i64(<vscale x 2 x double> [[MASKEDOFF:%.*]], <vscale x 2 x double>* [[TMP0]], <vscale x 2 x i8> [[BINDEX:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP1]]
|
|
//
|
|
vfloat64m2_t test_vluxei8_v_f64m2_m(vbool32_t mask, vfloat64m2_t maskedoff, const double *base, vuint8mf4_t bindex, size_t vl) {
|
|
return vluxei8(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_f64m4_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 4 x double>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x double> @llvm.riscv.vluxei.mask.nxv4f64.nxv4i8.i64(<vscale x 4 x double> [[MASKEDOFF:%.*]], <vscale x 4 x double>* [[TMP0]], <vscale x 4 x i8> [[BINDEX:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP1]]
|
|
//
|
|
vfloat64m4_t test_vluxei8_v_f64m4_m(vbool16_t mask, vfloat64m4_t maskedoff, const double *base, vuint8mf2_t bindex, size_t vl) {
|
|
return vluxei8(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei8_v_f64m8_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 8 x double>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x double> @llvm.riscv.vluxei.mask.nxv8f64.nxv8i8.i64(<vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x double>* [[TMP0]], <vscale x 8 x i8> [[BINDEX:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP1]]
|
|
//
|
|
vfloat64m8_t test_vluxei8_v_f64m8_m(vbool8_t mask, vfloat64m8_t maskedoff, const double *base, vuint8m1_t bindex, size_t vl) {
|
|
return vluxei8(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_f64m1_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 1 x double>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x double> @llvm.riscv.vluxei.mask.nxv1f64.nxv1i16.i64(<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x double>* [[TMP0]], <vscale x 1 x i16> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP1]]
|
|
//
|
|
vfloat64m1_t test_vluxei16_v_f64m1_m(vbool64_t mask, vfloat64m1_t maskedoff, const double *base, vuint16mf4_t bindex, size_t vl) {
|
|
return vluxei16(mask, maskedoff, base, bindex, vl);
|
|
}
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|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_f64m2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 2 x double>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x double> @llvm.riscv.vluxei.mask.nxv2f64.nxv2i16.i64(<vscale x 2 x double> [[MASKEDOFF:%.*]], <vscale x 2 x double>* [[TMP0]], <vscale x 2 x i16> [[BINDEX:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP1]]
|
|
//
|
|
vfloat64m2_t test_vluxei16_v_f64m2_m(vbool32_t mask, vfloat64m2_t maskedoff, const double *base, vuint16mf2_t bindex, size_t vl) {
|
|
return vluxei16(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_f64m4_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 4 x double>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x double> @llvm.riscv.vluxei.mask.nxv4f64.nxv4i16.i64(<vscale x 4 x double> [[MASKEDOFF:%.*]], <vscale x 4 x double>* [[TMP0]], <vscale x 4 x i16> [[BINDEX:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP1]]
|
|
//
|
|
vfloat64m4_t test_vluxei16_v_f64m4_m(vbool16_t mask, vfloat64m4_t maskedoff, const double *base, vuint16m1_t bindex, size_t vl) {
|
|
return vluxei16(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei16_v_f64m8_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 8 x double>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x double> @llvm.riscv.vluxei.mask.nxv8f64.nxv8i16.i64(<vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x double>* [[TMP0]], <vscale x 8 x i16> [[BINDEX:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP1]]
|
|
//
|
|
vfloat64m8_t test_vluxei16_v_f64m8_m(vbool8_t mask, vfloat64m8_t maskedoff, const double *base, vuint16m2_t bindex, size_t vl) {
|
|
return vluxei16(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_f64m1_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 1 x double>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x double> @llvm.riscv.vluxei.mask.nxv1f64.nxv1i32.i64(<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x double>* [[TMP0]], <vscale x 1 x i32> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP1]]
|
|
//
|
|
vfloat64m1_t test_vluxei32_v_f64m1_m(vbool64_t mask, vfloat64m1_t maskedoff, const double *base, vuint32mf2_t bindex, size_t vl) {
|
|
return vluxei32(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_f64m2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 2 x double>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x double> @llvm.riscv.vluxei.mask.nxv2f64.nxv2i32.i64(<vscale x 2 x double> [[MASKEDOFF:%.*]], <vscale x 2 x double>* [[TMP0]], <vscale x 2 x i32> [[BINDEX:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP1]]
|
|
//
|
|
vfloat64m2_t test_vluxei32_v_f64m2_m(vbool32_t mask, vfloat64m2_t maskedoff, const double *base, vuint32m1_t bindex, size_t vl) {
|
|
return vluxei32(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_f64m4_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 4 x double>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x double> @llvm.riscv.vluxei.mask.nxv4f64.nxv4i32.i64(<vscale x 4 x double> [[MASKEDOFF:%.*]], <vscale x 4 x double>* [[TMP0]], <vscale x 4 x i32> [[BINDEX:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP1]]
|
|
//
|
|
vfloat64m4_t test_vluxei32_v_f64m4_m(vbool16_t mask, vfloat64m4_t maskedoff, const double *base, vuint32m2_t bindex, size_t vl) {
|
|
return vluxei32(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei32_v_f64m8_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 8 x double>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x double> @llvm.riscv.vluxei.mask.nxv8f64.nxv8i32.i64(<vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x double>* [[TMP0]], <vscale x 8 x i32> [[BINDEX:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP1]]
|
|
//
|
|
vfloat64m8_t test_vluxei32_v_f64m8_m(vbool8_t mask, vfloat64m8_t maskedoff, const double *base, vuint32m4_t bindex, size_t vl) {
|
|
return vluxei32(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei64_v_f64m1_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 1 x double>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x double> @llvm.riscv.vluxei.mask.nxv1f64.nxv1i64.i64(<vscale x 1 x double> [[MASKEDOFF:%.*]], <vscale x 1 x double>* [[TMP0]], <vscale x 1 x i64> [[BINDEX:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP1]]
|
|
//
|
|
vfloat64m1_t test_vluxei64_v_f64m1_m(vbool64_t mask, vfloat64m1_t maskedoff, const double *base, vuint64m1_t bindex, size_t vl) {
|
|
return vluxei64(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei64_v_f64m2_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 2 x double>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x double> @llvm.riscv.vluxei.mask.nxv2f64.nxv2i64.i64(<vscale x 2 x double> [[MASKEDOFF:%.*]], <vscale x 2 x double>* [[TMP0]], <vscale x 2 x i64> [[BINDEX:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP1]]
|
|
//
|
|
vfloat64m2_t test_vluxei64_v_f64m2_m(vbool32_t mask, vfloat64m2_t maskedoff, const double *base, vuint64m2_t bindex, size_t vl) {
|
|
return vluxei64(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei64_v_f64m4_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 4 x double>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x double> @llvm.riscv.vluxei.mask.nxv4f64.nxv4i64.i64(<vscale x 4 x double> [[MASKEDOFF:%.*]], <vscale x 4 x double>* [[TMP0]], <vscale x 4 x i64> [[BINDEX:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP1]]
|
|
//
|
|
vfloat64m4_t test_vluxei64_v_f64m4_m(vbool16_t mask, vfloat64m4_t maskedoff, const double *base, vuint64m4_t bindex, size_t vl) {
|
|
return vluxei64(mask, maskedoff, base, bindex, vl);
|
|
}
|
|
|
|
// CHECK-RV64-LABEL: @test_vluxei64_v_f64m8_m(
|
|
// CHECK-RV64-NEXT: entry:
|
|
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 8 x double>*
|
|
// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x double> @llvm.riscv.vluxei.mask.nxv8f64.nxv8i64.i64(<vscale x 8 x double> [[MASKEDOFF:%.*]], <vscale x 8 x double>* [[TMP0]], <vscale x 8 x i64> [[BINDEX:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
|
|
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP1]]
|
|
//
|
|
vfloat64m8_t test_vluxei64_v_f64m8_m(vbool8_t mask, vfloat64m8_t maskedoff, const double *base, vuint64m8_t bindex, size_t vl) {
|
|
return vluxei64(mask, maskedoff, base, bindex, vl);
|
|
}
|