forked from OSchip/llvm-project
171 lines
9.4 KiB
C
171 lines
9.4 KiB
C
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
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// REQUIRES: riscv-registered-target
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// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
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// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
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#include <riscv_vector.h>
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// CHECK-RV64-LABEL: @test_vfwnmacc_vv_f64m1(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwnmacc.nxv1f64.nxv1f32.nxv1f32.i64(<vscale x 1 x double> [[ACC:%.*]], <vscale x 1 x float> [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
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//
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vfloat64m1_t test_vfwnmacc_vv_f64m1(vfloat64m1_t acc, vfloat32mf2_t op1,
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vfloat32mf2_t op2, size_t vl) {
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return vfwnmacc(acc, op1, op2, vl);
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}
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// CHECK-RV64-LABEL: @test_vfwnmacc_vf_f64m1(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwnmacc.nxv1f64.f32.nxv1f32.i64(<vscale x 1 x double> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
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//
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vfloat64m1_t test_vfwnmacc_vf_f64m1(vfloat64m1_t acc, float op1,
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vfloat32mf2_t op2, size_t vl) {
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return vfwnmacc(acc, op1, op2, vl);
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}
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// CHECK-RV64-LABEL: @test_vfwnmacc_vv_f64m2(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwnmacc.nxv2f64.nxv2f32.nxv2f32.i64(<vscale x 2 x double> [[ACC:%.*]], <vscale x 2 x float> [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
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//
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vfloat64m2_t test_vfwnmacc_vv_f64m2(vfloat64m2_t acc, vfloat32m1_t op1,
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vfloat32m1_t op2, size_t vl) {
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return vfwnmacc(acc, op1, op2, vl);
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}
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// CHECK-RV64-LABEL: @test_vfwnmacc_vf_f64m2(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwnmacc.nxv2f64.f32.nxv2f32.i64(<vscale x 2 x double> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
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//
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vfloat64m2_t test_vfwnmacc_vf_f64m2(vfloat64m2_t acc, float op1,
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vfloat32m1_t op2, size_t vl) {
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return vfwnmacc(acc, op1, op2, vl);
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}
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// CHECK-RV64-LABEL: @test_vfwnmacc_vv_f64m4(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwnmacc.nxv4f64.nxv4f32.nxv4f32.i64(<vscale x 4 x double> [[ACC:%.*]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
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//
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vfloat64m4_t test_vfwnmacc_vv_f64m4(vfloat64m4_t acc, vfloat32m2_t op1,
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vfloat32m2_t op2, size_t vl) {
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return vfwnmacc(acc, op1, op2, vl);
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}
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// CHECK-RV64-LABEL: @test_vfwnmacc_vf_f64m4(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwnmacc.nxv4f64.f32.nxv4f32.i64(<vscale x 4 x double> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
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//
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vfloat64m4_t test_vfwnmacc_vf_f64m4(vfloat64m4_t acc, float op1,
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vfloat32m2_t op2, size_t vl) {
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return vfwnmacc(acc, op1, op2, vl);
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}
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// CHECK-RV64-LABEL: @test_vfwnmacc_vv_f64m8(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwnmacc.nxv8f64.nxv8f32.nxv8f32.i64(<vscale x 8 x double> [[ACC:%.*]], <vscale x 8 x float> [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
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//
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vfloat64m8_t test_vfwnmacc_vv_f64m8(vfloat64m8_t acc, vfloat32m4_t op1,
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vfloat32m4_t op2, size_t vl) {
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return vfwnmacc(acc, op1, op2, vl);
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}
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// CHECK-RV64-LABEL: @test_vfwnmacc_vf_f64m8(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwnmacc.nxv8f64.f32.nxv8f32.i64(<vscale x 8 x double> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
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//
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vfloat64m8_t test_vfwnmacc_vf_f64m8(vfloat64m8_t acc, float op1,
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vfloat32m4_t op2, size_t vl) {
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return vfwnmacc(acc, op1, op2, vl);
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}
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// CHECK-RV64-LABEL: @test_vfwnmacc_vv_f64m1_m(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwnmacc.mask.nxv1f64.nxv1f32.nxv1f32.i64(<vscale x 1 x double> [[ACC:%.*]], <vscale x 1 x float> [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
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//
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vfloat64m1_t test_vfwnmacc_vv_f64m1_m(vbool64_t mask, vfloat64m1_t acc,
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vfloat32mf2_t op1, vfloat32mf2_t op2,
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size_t vl) {
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return vfwnmacc(mask, acc, op1, op2, vl);
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}
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// CHECK-RV64-LABEL: @test_vfwnmacc_vf_f64m1_m(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwnmacc.mask.nxv1f64.f32.nxv1f32.i64(<vscale x 1 x double> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 1 x float> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
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//
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vfloat64m1_t test_vfwnmacc_vf_f64m1_m(vbool64_t mask, vfloat64m1_t acc,
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float op1, vfloat32mf2_t op2, size_t vl) {
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return vfwnmacc(mask, acc, op1, op2, vl);
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}
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// CHECK-RV64-LABEL: @test_vfwnmacc_vv_f64m2_m(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwnmacc.mask.nxv2f64.nxv2f32.nxv2f32.i64(<vscale x 2 x double> [[ACC:%.*]], <vscale x 2 x float> [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
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//
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vfloat64m2_t test_vfwnmacc_vv_f64m2_m(vbool32_t mask, vfloat64m2_t acc,
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vfloat32m1_t op1, vfloat32m1_t op2,
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size_t vl) {
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return vfwnmacc(mask, acc, op1, op2, vl);
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}
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// CHECK-RV64-LABEL: @test_vfwnmacc_vf_f64m2_m(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfwnmacc.mask.nxv2f64.f32.nxv2f32.i64(<vscale x 2 x double> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 2 x float> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
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//
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vfloat64m2_t test_vfwnmacc_vf_f64m2_m(vbool32_t mask, vfloat64m2_t acc,
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float op1, vfloat32m1_t op2, size_t vl) {
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return vfwnmacc(mask, acc, op1, op2, vl);
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}
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// CHECK-RV64-LABEL: @test_vfwnmacc_vv_f64m4_m(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwnmacc.mask.nxv4f64.nxv4f32.nxv4f32.i64(<vscale x 4 x double> [[ACC:%.*]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
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//
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vfloat64m4_t test_vfwnmacc_vv_f64m4_m(vbool16_t mask, vfloat64m4_t acc,
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vfloat32m2_t op1, vfloat32m2_t op2,
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size_t vl) {
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return vfwnmacc(mask, acc, op1, op2, vl);
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}
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// CHECK-RV64-LABEL: @test_vfwnmacc_vf_f64m4_m(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfwnmacc.mask.nxv4f64.f32.nxv4f32.i64(<vscale x 4 x double> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
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//
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vfloat64m4_t test_vfwnmacc_vf_f64m4_m(vbool16_t mask, vfloat64m4_t acc,
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float op1, vfloat32m2_t op2, size_t vl) {
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return vfwnmacc(mask, acc, op1, op2, vl);
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}
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// CHECK-RV64-LABEL: @test_vfwnmacc_vv_f64m8_m(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwnmacc.mask.nxv8f64.nxv8f32.nxv8f32.i64(<vscale x 8 x double> [[ACC:%.*]], <vscale x 8 x float> [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
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//
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vfloat64m8_t test_vfwnmacc_vv_f64m8_m(vbool8_t mask, vfloat64m8_t acc,
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vfloat32m4_t op1, vfloat32m4_t op2,
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size_t vl) {
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return vfwnmacc(mask, acc, op1, op2, vl);
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}
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// CHECK-RV64-LABEL: @test_vfwnmacc_vf_f64m8_m(
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfwnmacc.mask.nxv8f64.f32.nxv8f32.i64(<vscale x 8 x double> [[ACC:%.*]], float [[OP1:%.*]], <vscale x 8 x float> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
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// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
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//
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vfloat64m8_t test_vfwnmacc_vf_f64m8_m(vbool8_t mask, vfloat64m8_t acc,
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float op1, vfloat32m4_t op2, size_t vl) {
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return vfwnmacc(mask, acc, op1, op2, vl);
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}
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