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rvb-intrinsics
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[RISCV] [1/2] Add IR intrinsic for Zbe extension
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2021-04-25 19:14:34 -07:00 |
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rvv-intrinsics
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[RISCV] After reverting _mt builtins, add `ta` argument for LLVM IR.
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2021-10-13 19:41:49 +08:00 |
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rvv-intrinsics-overloaded
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[RISCV] After reverting _mt builtins, add `ta` argument for LLVM IR.
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2021-10-13 19:41:49 +08:00 |
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riscv-atomics.c
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NFC: update clang tests to check ordering and alignment for atomicrmw/cmpxchg.
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2021-02-11 17:35:09 -05:00 |
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riscv-attr-builtin-alias-err.c
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[Clang] Add clang attribute `clang_builtin_alias`.
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2021-04-25 08:49:19 +08:00 |
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riscv-attr-builtin-alias.c
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[Clang] Add clang attribute `clang_builtin_alias`.
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2021-04-25 08:49:19 +08:00 |
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riscv-inline-asm-rvv.c
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[RISCV] Rename vector inline constraint from 'v' to 'vr' and 'vm' in IR.
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2021-08-01 05:58:17 +08:00 |
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riscv-inline-asm.c
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Revert D105169 due to the two-stage failure in ASAN
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2021-10-18 23:52:46 +09:00 |
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riscv-metadata.c
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…
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riscv-sdata-module-flag.c
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…
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riscv-v-debuginfo.c
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[Clang][RISCV] Define RISC-V V builtin types
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2021-02-18 10:17:31 +08:00 |
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riscv-v-lifetime.cpp
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[Clang][CodeGen] Set the size of llvm.lifetime to unknown for scalable types.
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2021-06-07 23:30:13 +08:00 |
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riscv32-ilp32-abi.c
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Revert D105169 due to the two-stage failure in ASAN
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2021-10-18 23:52:46 +09:00 |
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riscv32-ilp32-ilp32f-abi.c
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Revert D105169 due to the two-stage failure in ASAN
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2021-10-18 23:52:46 +09:00 |
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riscv32-ilp32-ilp32f-ilp32d-abi.c
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Revert D105169 due to the two-stage failure in ASAN
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2021-10-18 23:52:46 +09:00 |
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riscv32-ilp32d-abi.c
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Revert D105169 due to the two-stage failure in ASAN
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2021-10-18 23:52:46 +09:00 |
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riscv32-ilp32f-abi.c
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Revert D105169 due to the two-stage failure in ASAN
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2021-10-18 23:52:46 +09:00 |
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riscv32-ilp32f-ilp32d-abi.c
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Revert D105169 due to the two-stage failure in ASAN
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2021-10-18 23:52:46 +09:00 |
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riscv64-lp64-abi.c
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Revert D105169 due to the two-stage failure in ASAN
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2021-10-18 23:52:46 +09:00 |
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riscv64-lp64-lp64f-abi.c
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Revert D105169 due to the two-stage failure in ASAN
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2021-10-18 23:52:46 +09:00 |
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riscv64-lp64-lp64f-lp64d-abi.c
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Revert D105169 due to the two-stage failure in ASAN
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2021-10-18 23:52:46 +09:00 |
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riscv64-lp64d-abi.c
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Revert D105169 due to the two-stage failure in ASAN
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2021-10-18 23:52:46 +09:00 |
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riscv64-lp64f-lp64d-abi.c
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Revert D105169 due to the two-stage failure in ASAN
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2021-10-18 23:52:46 +09:00 |
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rvv_errors.c
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[RISCV] Validate the SEW and LMUL operands to __builtin_rvv_vsetvli(max)
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2021-05-10 12:11:13 -07:00 |
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