forked from OSchip/llvm-project
154 lines
5.6 KiB
C
154 lines
5.6 KiB
C
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
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// RUN: %clang_cc1 -triple armv8.6a-arm-none-eabi -target-feature +neon -target-feature +bf16 -mfloat-abi hard \
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// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg -instcombine | FileCheck %s
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// RUN: %clang_cc1 -triple armv8.6a-arm-none-eabi -target-feature +neon -target-feature +bf16 -mfloat-abi soft \
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// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg -instcombine | FileCheck %s
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#include <arm_neon.h>
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// CHECK-LABEL: @test_vcreate_bf16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A:%.*]] to <4 x bfloat>
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// CHECK-NEXT: ret <4 x bfloat> [[TMP0]]
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//
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bfloat16x4_t test_vcreate_bf16(uint64_t a) {
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return vcreate_bf16(a);
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}
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// CHECK-LABEL: @test_vdup_n_bf16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x bfloat> undef, bfloat [[V:%.*]], i32 0
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// CHECK-NEXT: [[VECINIT3_I:%.*]] = shufflevector <4 x bfloat> [[VECINIT_I]], <4 x bfloat> undef, <4 x i32> zeroinitializer
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// CHECK-NEXT: ret <4 x bfloat> [[VECINIT3_I]]
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//
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bfloat16x4_t test_vdup_n_bf16(bfloat16_t v) {
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return vdup_n_bf16(v);
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}
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// CHECK-LABEL: @test_vdupq_n_bf16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <8 x bfloat> undef, bfloat [[V:%.*]], i32 0
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// CHECK-NEXT: [[VECINIT7_I:%.*]] = shufflevector <8 x bfloat> [[VECINIT_I]], <8 x bfloat> undef, <8 x i32> zeroinitializer
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// CHECK-NEXT: ret <8 x bfloat> [[VECINIT7_I]]
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//
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bfloat16x8_t test_vdupq_n_bf16(bfloat16_t v) {
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return vdupq_n_bf16(v);
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}
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// CHECK-LABEL: @test_vdup_lane_bf16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[LANE:%.*]] = shufflevector <4 x bfloat> [[V:%.*]], <4 x bfloat> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
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// CHECK-NEXT: ret <4 x bfloat> [[LANE]]
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//
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bfloat16x4_t test_vdup_lane_bf16(bfloat16x4_t v) {
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return vdup_lane_bf16(v, 1);
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}
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// CHECK-LABEL: @test_vdupq_lane_bf16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[LANE:%.*]] = shufflevector <4 x bfloat> [[V:%.*]], <4 x bfloat> undef, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
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// CHECK-NEXT: ret <8 x bfloat> [[LANE]]
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//
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bfloat16x8_t test_vdupq_lane_bf16(bfloat16x4_t v) {
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return vdupq_lane_bf16(v, 1);
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}
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// CHECK-LABEL: @test_vdup_laneq_bf16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[LANE:%.*]] = shufflevector <8 x bfloat> [[V:%.*]], <8 x bfloat> undef, <4 x i32> <i32 7, i32 7, i32 7, i32 7>
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// CHECK-NEXT: ret <4 x bfloat> [[LANE]]
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//
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bfloat16x4_t test_vdup_laneq_bf16(bfloat16x8_t v) {
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return vdup_laneq_bf16(v, 7);
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}
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// CHECK-LABEL: @test_vdupq_laneq_bf16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[LANE:%.*]] = shufflevector <8 x bfloat> [[V:%.*]], <8 x bfloat> undef, <8 x i32> <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7>
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// CHECK-NEXT: ret <8 x bfloat> [[LANE]]
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//
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bfloat16x8_t test_vdupq_laneq_bf16(bfloat16x8_t v) {
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return vdupq_laneq_bf16(v, 7);
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}
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// CHECK-LABEL: @test_vcombine_bf16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x bfloat> [[LOW:%.*]], <4 x bfloat> [[HIGH:%.*]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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// CHECK-NEXT: ret <8 x bfloat> [[SHUFFLE_I]]
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//
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bfloat16x8_t test_vcombine_bf16(bfloat16x4_t low, bfloat16x4_t high) {
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return vcombine_bf16(low, high);
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}
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// CHECK-LABEL: @test_vget_high_bf16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x bfloat> [[A:%.*]], <8 x bfloat> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
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// CHECK-NEXT: ret <4 x bfloat> [[SHUFFLE_I]]
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//
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bfloat16x4_t test_vget_high_bf16(bfloat16x8_t a) {
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return vget_high_bf16(a);
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}
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// CHECK-LABEL: @test_vget_low_bf16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x bfloat> [[A:%.*]], <8 x bfloat> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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// CHECK-NEXT: ret <4 x bfloat> [[SHUFFLE_I]]
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//
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bfloat16x4_t test_vget_low_bf16(bfloat16x8_t a) {
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return vget_low_bf16(a);
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}
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// CHECK-LABEL: @test_vget_lane_bf16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[VGET_LANE:%.*]] = extractelement <4 x bfloat> [[V:%.*]], i32 1
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// CHECK-NEXT: ret bfloat [[VGET_LANE]]
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//
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bfloat16_t test_vget_lane_bf16(bfloat16x4_t v) {
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return vget_lane_bf16(v, 1);
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}
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// CHECK-LABEL: @test_vgetq_lane_bf16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[VGET_LANE:%.*]] = extractelement <8 x bfloat> [[V:%.*]], i32 7
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// CHECK-NEXT: ret bfloat [[VGET_LANE]]
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//
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bfloat16_t test_vgetq_lane_bf16(bfloat16x8_t v) {
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return vgetq_lane_bf16(v, 7);
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}
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// CHECK-LABEL: @test_vset_lane_bf16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[VSET_LANE:%.*]] = insertelement <4 x bfloat> [[V:%.*]], bfloat [[A:%.*]], i32 1
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// CHECK-NEXT: ret <4 x bfloat> [[VSET_LANE]]
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//
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bfloat16x4_t test_vset_lane_bf16(bfloat16_t a, bfloat16x4_t v) {
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return vset_lane_bf16(a, v, 1);
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}
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// CHECK-LABEL: @test_vsetq_lane_bf16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[VSET_LANE:%.*]] = insertelement <8 x bfloat> [[V:%.*]], bfloat [[A:%.*]], i32 7
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// CHECK-NEXT: ret <8 x bfloat> [[VSET_LANE]]
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//
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bfloat16x8_t test_vsetq_lane_bf16(bfloat16_t a, bfloat16x8_t v) {
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return vsetq_lane_bf16(a, v, 7);
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}
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// CHECK-LABEL: @test_vduph_lane_bf16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[VGET_LANE:%.*]] = extractelement <4 x bfloat> [[V:%.*]], i32 1
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// CHECK-NEXT: ret bfloat [[VGET_LANE]]
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//
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bfloat16_t test_vduph_lane_bf16(bfloat16x4_t v) {
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return vduph_lane_bf16(v, 1);
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}
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// CHECK-LABEL: @test_vduph_laneq_bf16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[VGET_LANE:%.*]] = extractelement <8 x bfloat> [[V:%.*]], i32 7
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// CHECK-NEXT: ret bfloat [[VGET_LANE]]
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//
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bfloat16_t test_vduph_laneq_bf16(bfloat16x8_t v) {
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return vduph_laneq_bf16(v, 7);
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}
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