llvm-project/llvm
Quentin Colombet 4a6b75012d [RegisterBankInfo] Cache the getMinimalPhysRegClass information
TargetRegisterInfo::getMinimalPhysRegClass is actually pretty expensive
because it has to iterate over all the register classes.
Cache this information as we need and get it so that we limit its usage.
Right now, we heavily rely on it, because this is how we get the mapping
for vregs defined by copies from physreg (i.e., the one that are ABI
related).

Improve compile time by up to 10% for that pass.

NFC

llvm-svn: 315759
2017-10-13 21:16:15 +00:00
..
bindings [dump] Remove NDEBUG from test to enable dump methods [NFC] 2017-10-12 16:16:06 +00:00
cmake [cmake] Allow building fuzzers with OSS-Fuzz flags. 2017-10-12 21:58:41 +00:00
docs [llvm-demangle-fuzzer] Add a fuzz target for ItaniumDemangler. 2017-10-13 17:35:37 +00:00
examples
include [RegisterBankInfo] Cache the getMinimalPhysRegClass information 2017-10-13 21:16:15 +00:00
lib [RegisterBankInfo] Cache the getMinimalPhysRegClass information 2017-10-13 21:16:15 +00:00
projects
resources
runtimes
test AMDGPU: Implement hasBitPreservingFPLogic 2017-10-13 21:10:22 +00:00
tools [llvm-demangle-fuzzer] Add a fuzz target for ItaniumDemangler. 2017-10-13 17:35:37 +00:00
unittests [SCEV] Maintain and use a loop->loop invalidation dependency 2017-10-13 17:13:44 +00:00
utils [aarch64] Support APInt and APFloat in ImmLeaf subclasses and make AArch64 use them. 2017-10-13 20:42:18 +00:00
.arcconfig
.clang-format
.clang-tidy
.gitignore
CMakeLists.txt [cmake] Allow building fuzzers with OSS-Fuzz flags. 2017-10-12 21:58:41 +00:00
CODE_OWNERS.TXT
CREDITS.TXT Add myself to CREDITS.txt 2017-09-18 14:33:39 +00:00
LICENSE.TXT
LLVMBuild.txt
README.txt
RELEASE_TESTERS.TXT
configure
llvm.spec.in

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