Dmitry Preobrazhensky 167f8b69e3 [AMDGPU][MC] Corrected several VI opcodes to avoid printing _e64 ... See bug 32936: https://bugs.llvm.org//show_bug.cgi?id=32936 Reviewers: artem.tamazov, vpykhtin Differential Revision: https://reviews.llvm.org/D33123 llvm-svn: 303070		2017-05-15 14:28:23 +00:00
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AArch64	[AArch64] armv8-A doesn't have CRC.	2017-05-03 20:33:52 +00:00
AMDGPU	[AMDGPU][MC] Corrected several VI opcodes to avoid printing _e64	2017-05-15 14:28:23 +00:00
ARM	[ARM] Saturation instructions are DSP-only	2016-07-25 22:25:25 +00:00
Hexagon	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
Lanai	[lanai] Add Lanai backend.	2016-03-28 13:09:54 +00:00
Mips	[mips] Correct c.cond.fmt instruction definition.	2017-01-16 13:55:58 +00:00
PowerPC	[PPC] Change the register constraint of the first source operand of instruction mtvsrdd to g8rc_nox0	2017-05-11 22:17:35 +00:00
Sparc	This change adds co-processor condition branching and conditional traps to the Sparc back-end.	2016-03-09 18:20:21 +00:00
SystemZ	[SystemZ] Add miscellaneous instructions	2017-05-10 14:20:15 +00:00
X86	[X86][LWP] Add llvm support for LWP instructions (reapplied).	2017-05-03 15:51:39 +00:00
XCore	…