forked from OSchip/llvm-project
274 lines
7.7 KiB
LLVM
274 lines
7.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=riscv32 \
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; RUN: | FileCheck %s --check-prefixes=CHECK,RV32,RV32I
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; RUN: llc < %s -mtriple=riscv64 \
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; RUN: | FileCheck %s --check-prefixes=CHECK,RV64,RV64I
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; RUN: llc < %s -mtriple=riscv32 -mattr=+experimental-zbb \
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; RUN: | FileCheck %s --check-prefixes=CHECK,RV32,RV32ZBB
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; RUN: llc < %s -mtriple=riscv64 -mattr=+experimental-zbb \
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; RUN: | FileCheck %s --check-prefixes=CHECK,RV64,RV64ZBB
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; Compare if negative and select of constants where one constant is zero.
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define i32 @neg_sel_constants(i32 signext %a) {
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; RV32-LABEL: neg_sel_constants:
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; RV32: # %bb.0:
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; RV32-NEXT: srai a0, a0, 31
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; RV32-NEXT: andi a0, a0, 5
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; RV32-NEXT: ret
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;
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; RV64-LABEL: neg_sel_constants:
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; RV64: # %bb.0:
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; RV64-NEXT: srai a0, a0, 63
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; RV64-NEXT: andi a0, a0, 5
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; RV64-NEXT: ret
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%tmp.1 = icmp slt i32 %a, 0
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%retval = select i1 %tmp.1, i32 5, i32 0
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ret i32 %retval
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}
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; Compare if negative and select of constants where one constant is zero and the
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; other is a single bit.
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define i32 @neg_sel_special_constant(i32 signext %a) {
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; RV32-LABEL: neg_sel_special_constant:
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; RV32: # %bb.0:
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; RV32-NEXT: srli a0, a0, 22
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; RV32-NEXT: andi a0, a0, 512
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; RV32-NEXT: ret
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;
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; RV64-LABEL: neg_sel_special_constant:
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; RV64: # %bb.0:
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; RV64-NEXT: addi a1, zero, 1
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; RV64-NEXT: slli a1, a1, 31
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; RV64-NEXT: and a0, a0, a1
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; RV64-NEXT: srli a0, a0, 22
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; RV64-NEXT: ret
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%tmp.1 = icmp slt i32 %a, 0
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%retval = select i1 %tmp.1, i32 512, i32 0
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ret i32 %retval
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}
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; Compare if negative and select variable or zero.
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define i32 @neg_sel_variable_and_zero(i32 signext %a, i32 signext %b) {
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; CHECK-LABEL: neg_sel_variable_and_zero:
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; CHECK: # %bb.0:
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; CHECK-NEXT: srai a0, a0, 31
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; CHECK-NEXT: and a0, a0, a1
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; CHECK-NEXT: ret
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%tmp.1 = icmp slt i32 %a, 0
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%retval = select i1 %tmp.1, i32 %b, i32 0
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ret i32 %retval
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}
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; Compare if not positive and select the same variable as being compared:
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; smin(a, 0).
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define i32 @not_pos_sel_same_variable(i32 signext %a) {
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; CHECK-LABEL: not_pos_sel_same_variable:
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; CHECK: # %bb.0:
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; CHECK-NEXT: srai a1, a0, 31
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; CHECK-NEXT: and a0, a1, a0
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; CHECK-NEXT: ret
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%tmp = icmp slt i32 %a, 1
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%min = select i1 %tmp, i32 %a, i32 0
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ret i32 %min
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}
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; Flipping the comparison condition can be handled by getting the bitwise not of
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; the sign mask.
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; TODO: We aren't doing a good job of this.
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; Compare if positive and select of constants where one constant is zero.
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define i32 @pos_sel_constants(i32 signext %a) {
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; CHECK-LABEL: pos_sel_constants:
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; CHECK: # %bb.0:
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; CHECK-NEXT: mv a1, a0
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; CHECK-NEXT: addi a0, zero, 5
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; CHECK-NEXT: bgez a1, .LBB4_2
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: mv a0, zero
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; CHECK-NEXT: .LBB4_2:
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; CHECK-NEXT: ret
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%tmp.1 = icmp sgt i32 %a, -1
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%retval = select i1 %tmp.1, i32 5, i32 0
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ret i32 %retval
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}
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; Compare if positive and select of constants where one constant is zero and the
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; other is a single bit.
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; TODO: Why do RV32 and RV64 generate different code? RV64 uses more registers,
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; but the addi isn't part of the dependency chain of %a so may be faster.
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define i32 @pos_sel_special_constant(i32 signext %a) {
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; RV32-LABEL: pos_sel_special_constant:
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; RV32: # %bb.0:
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; RV32-NEXT: not a0, a0
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; RV32-NEXT: srli a0, a0, 22
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; RV32-NEXT: andi a0, a0, 512
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; RV32-NEXT: ret
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;
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; RV64-LABEL: pos_sel_special_constant:
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; RV64: # %bb.0:
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; RV64-NEXT: addi a1, zero, -1
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; RV64-NEXT: slt a0, a1, a0
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; RV64-NEXT: slli a0, a0, 9
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; RV64-NEXT: ret
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%tmp.1 = icmp sgt i32 %a, -1
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%retval = select i1 %tmp.1, i32 512, i32 0
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ret i32 %retval
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}
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; Compare if positive and select variable or zero.
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define i32 @pos_sel_variable_and_zero(i32 signext %a, i32 signext %b) {
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; RV32I-LABEL: pos_sel_variable_and_zero:
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; RV32I: # %bb.0:
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; RV32I-NEXT: bgez a0, .LBB6_2
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: mv a1, zero
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; RV32I-NEXT: .LBB6_2:
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; RV32I-NEXT: mv a0, a1
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: pos_sel_variable_and_zero:
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; RV64I: # %bb.0:
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; RV64I-NEXT: bgez a0, .LBB6_2
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; RV64I-NEXT: # %bb.1:
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; RV64I-NEXT: mv a1, zero
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; RV64I-NEXT: .LBB6_2:
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; RV64I-NEXT: mv a0, a1
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; RV64I-NEXT: ret
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;
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; RV32ZBB-LABEL: pos_sel_variable_and_zero:
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; RV32ZBB: # %bb.0:
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; RV32ZBB-NEXT: srai a0, a0, 31
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; RV32ZBB-NEXT: andn a0, a1, a0
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; RV32ZBB-NEXT: ret
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;
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; RV64ZBB-LABEL: pos_sel_variable_and_zero:
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; RV64ZBB: # %bb.0:
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; RV64ZBB-NEXT: srai a0, a0, 31
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; RV64ZBB-NEXT: andn a0, a1, a0
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; RV64ZBB-NEXT: ret
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%tmp.1 = icmp sgt i32 %a, -1
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%retval = select i1 %tmp.1, i32 %b, i32 0
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ret i32 %retval
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}
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; Compare if not negative or zero and select the same variable as being
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; compared: smax(a, 0).
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define i32 @not_neg_sel_same_variable(i32 signext %a) {
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; RV32I-LABEL: not_neg_sel_same_variable:
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; RV32I: # %bb.0:
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; RV32I-NEXT: bgtz a0, .LBB7_2
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: mv a0, zero
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; RV32I-NEXT: .LBB7_2:
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: not_neg_sel_same_variable:
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; RV64I: # %bb.0:
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; RV64I-NEXT: bgtz a0, .LBB7_2
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; RV64I-NEXT: # %bb.1:
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; RV64I-NEXT: mv a0, zero
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; RV64I-NEXT: .LBB7_2:
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; RV64I-NEXT: ret
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;
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; RV32ZBB-LABEL: not_neg_sel_same_variable:
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; RV32ZBB: # %bb.0:
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; RV32ZBB-NEXT: max a0, a0, zero
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; RV32ZBB-NEXT: ret
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;
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; RV64ZBB-LABEL: not_neg_sel_same_variable:
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; RV64ZBB: # %bb.0:
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; RV64ZBB-NEXT: max a0, a0, zero
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; RV64ZBB-NEXT: ret
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%tmp = icmp sgt i32 %a, 0
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%min = select i1 %tmp, i32 %a, i32 0
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ret i32 %min
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}
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; ret = (x-y) > 0 ? x-y : 0
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define i32 @sub_clamp_zero(i32 signext %x, i32 signext %y) {
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; RV32I-LABEL: sub_clamp_zero:
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; RV32I: # %bb.0:
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; RV32I-NEXT: sub a0, a0, a1
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; RV32I-NEXT: bgtz a0, .LBB8_2
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: mv a0, zero
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; RV32I-NEXT: .LBB8_2:
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: sub_clamp_zero:
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; RV64I: # %bb.0:
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; RV64I-NEXT: subw a0, a0, a1
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; RV64I-NEXT: bgtz a0, .LBB8_2
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; RV64I-NEXT: # %bb.1:
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; RV64I-NEXT: mv a0, zero
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; RV64I-NEXT: .LBB8_2:
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; RV64I-NEXT: ret
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;
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; RV32ZBB-LABEL: sub_clamp_zero:
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; RV32ZBB: # %bb.0:
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; RV32ZBB-NEXT: sub a0, a0, a1
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; RV32ZBB-NEXT: max a0, a0, zero
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; RV32ZBB-NEXT: ret
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;
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; RV64ZBB-LABEL: sub_clamp_zero:
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; RV64ZBB: # %bb.0:
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; RV64ZBB-NEXT: subw a0, a0, a1
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; RV64ZBB-NEXT: max a0, a0, zero
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; RV64ZBB-NEXT: ret
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%sub = sub nsw i32 %x, %y
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%cmp = icmp sgt i32 %sub, 0
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%sel = select i1 %cmp, i32 %sub, i32 0
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ret i32 %sel
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}
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define i8 @sel_shift_bool_i8(i1 %t) {
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; CHECK-LABEL: sel_shift_bool_i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: andi a1, a0, 1
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; CHECK-NEXT: addi a0, zero, -128
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; CHECK-NEXT: bnez a1, .LBB9_2
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: mv a0, zero
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; CHECK-NEXT: .LBB9_2:
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; CHECK-NEXT: ret
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%shl = select i1 %t, i8 128, i8 0
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ret i8 %shl
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}
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define i16 @sel_shift_bool_i16(i1 %t) {
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; CHECK-LABEL: sel_shift_bool_i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: andi a0, a0, 1
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; CHECK-NEXT: slli a0, a0, 7
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; CHECK-NEXT: ret
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%shl = select i1 %t, i16 128, i16 0
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ret i16 %shl
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}
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define i32 @sel_shift_bool_i32(i1 %t) {
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; CHECK-LABEL: sel_shift_bool_i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: andi a0, a0, 1
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; CHECK-NEXT: slli a0, a0, 6
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; CHECK-NEXT: ret
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%shl = select i1 %t, i32 64, i32 0
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ret i32 %shl
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}
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define i64 @sel_shift_bool_i64(i1 %t) {
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; RV32-LABEL: sel_shift_bool_i64:
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; RV32: # %bb.0:
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; RV32-NEXT: andi a0, a0, 1
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; RV32-NEXT: slli a0, a0, 16
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; RV32-NEXT: mv a1, zero
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; RV32-NEXT: ret
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;
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; RV64-LABEL: sel_shift_bool_i64:
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; RV64: # %bb.0:
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; RV64-NEXT: andi a0, a0, 1
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; RV64-NEXT: slli a0, a0, 16
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; RV64-NEXT: ret
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%shl = select i1 %t, i64 65536, i64 0
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ret i64 %shl
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}
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