forked from OSchip/llvm-project
37 lines
1.0 KiB
LLVM
37 lines
1.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbc -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV32ZBC
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declare i32 @llvm.riscv.clmul.i32(i32 %a, i32 %b)
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define i32 @clmul32(i32 %a, i32 %b) nounwind {
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; RV32ZBC-LABEL: clmul32:
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; RV32ZBC: # %bb.0:
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; RV32ZBC-NEXT: clmul a0, a0, a1
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; RV32ZBC-NEXT: ret
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%tmp = call i32 @llvm.riscv.clmul.i32(i32 %a, i32 %b)
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ret i32 %tmp
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}
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declare i32 @llvm.riscv.clmulh.i32(i32 %a, i32 %b)
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define i32 @clmul32h(i32 %a, i32 %b) nounwind {
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; RV32ZBC-LABEL: clmul32h:
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; RV32ZBC: # %bb.0:
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; RV32ZBC-NEXT: clmulh a0, a0, a1
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; RV32ZBC-NEXT: ret
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%tmp = call i32 @llvm.riscv.clmulh.i32(i32 %a, i32 %b)
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ret i32 %tmp
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}
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declare i32 @llvm.riscv.clmulr.i32(i32 %a, i32 %b)
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define i32 @clmul32r(i32 %a, i32 %b) nounwind {
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; RV32ZBC-LABEL: clmul32r:
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; RV32ZBC: # %bb.0:
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; RV32ZBC-NEXT: clmulr a0, a0, a1
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; RV32ZBC-NEXT: ret
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%tmp = call i32 @llvm.riscv.clmulr.i32(i32 %a, i32 %b)
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ret i32 %tmp
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}
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