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llvm-project/llvm/test/CodeGen/RISCV
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Philipp Tomsich af57a71d18 [RISCV] Don't call setHasMultipleConditionRegisters(), so icmp is sunk 
On RISC-V, icmp is not sunk (as the following snippet shows) which
generates the following suboptimal branch pattern:
```
  core_list_find:
	lh	a2, 2(a1)
	seqz	a3, a0         <<
	bltz	a2, .LBB0_5
	bnez	a3, .LBB0_9    << should sink the seqz
        [...]
	j	.LBB0_9
  .LBB0_5:
	bnez	a3, .LBB0_9    << should sink the seqz
	lh	a1, 0(a1)
        [...]
```
due to an icmp not being sunk.

The blocks after `codegenprepare` look as follows:
```
  define dso_local %struct.list_head_s* @core_list_find(%struct.list_head_s* readonly %list, %struct.list_data_s* nocapture readonly %info) local_unnamed_addr #0 {
  entry:
    %idx = getelementptr inbounds %struct.list_data_s, %struct.list_data_s* %info, i64 0, i32 1
    %0 = load i16, i16* %idx, align 2, !tbaa !4
    %cmp = icmp sgt i16 %0, -1
    %tobool.not37 = icmp eq %struct.list_head_s* %list, null
    br i1 %cmp, label %while.cond.preheader, label %while.cond9.preheader

  while.cond9.preheader:                            ; preds = %entry
    br i1 %tobool.not37, label %return, label %land.rhs11.lr.ph
```
where the `%tobool.not37` is the result of the icmp that is not sunk.
Note that it is computed in the basic-block up until what becomes the
`bltz` instruction and the `bnez` is a basic-block of its own.

Compare this to what happens on AArch64 (where the icmp is correctly sunk):
```
  define dso_local %struct.list_head_s* @core_list_find(%struct.list_head_s* readonly %list, %struct.list_data_s* nocapture readonly %info) local_unnamed_addr #0 {
  entry:
    %idx = getelementptr inbounds %struct.list_data_s, %struct.list_data_s* %info, i64 0, i32 1
    %0 = load i16, i16* %idx, align 2, !tbaa !6
    %cmp = icmp sgt i16 %0, -1
    br i1 %cmp, label %while.cond.preheader, label %while.cond9.preheader

  while.cond9.preheader:                            ; preds = %entry
    %1 = icmp eq %struct.list_head_s* %list, null
    br i1 %1, label %return, label %land.rhs11.lr.ph
```

This is caused by sinkCmpExpression() being skipped, if multiple
condition registers are supported.

Given that the check for multiple condition registers affect only
sinkCmpExpression() and shouldNormalizeToSelectSequence(), this change
adjusts the RISC-V target as follows:
 * we no longer signal multiple condition registers (thus changing
   the behaviour of sinkCmpExpression() back to sinking the icmp)
 * we override shouldNormalizeToSelectSequence() to let always select
   the preferred normalisation strategy for our backend

With both changes, the test results remain unchanged.  Note that without
the target-specific override to shouldNormalizeToSelectSequence(), there
is worse code (more branches) generated for select-and.ll and select-or.ll.

The original test case changes as expected:
```
  core_list_find:
	lh	a2, 2(a1)
	bltz	a2, .LBB0_5
	beqz	a0, .LBB0_9    <<
        [...]
	j	.LBB0_9
.LBB0_5:
	beqz	a0, .LBB0_9    <<
	lh	a1, 0(a1)
        [...]
```

Differential Revision: https://reviews.llvm.org/D98932
 		2021-11-19 08:32:59 -08:00
..
GlobalISel [RISCV] Reorder the vector register allocation order. 2021-10-19 09:30:13 +08:00
intrinsics
…
rvv [AArch64][RISCV] Fix expected smulo/umulo test output 2021-11-18 11:57:26 +00:00
MachineSink-implicit-x0.mir Fix minor deficiency in machine-sink. 2021-11-12 08:01:13 +01:00
add-before-shl.ll [RISCV] Teach isel to select ADDW/SUBW/MULW/SLLIW when only the lower 32-bits are used. 2021-08-18 10:22:00 -07:00
add-imm.ll [RISCV] Remove sext_inreg+add/sub/mul/shl isel patterns. 2021-08-18 11:07:11 -07:00
addc-adde-sube-subc.ll
…
addcarry.ll
…
addimm-mulimm.ll [RISCV] Optimize (add (mul r, c0), c1) 2021-11-08 02:58:25 +00:00
addrspacecast.ll [RISCV] Assume no-op addrspacecasts by default 2020-12-18 21:03:37 +00:00
aext-to-sext.ll [RISCV] Protect the SHL/SRA/SRL handlers in LowerOperation against being called for an illegal i32 shift amount. 2021-06-29 09:45:13 -07:00
align-loops.ll [CodeGen] Add -align-loops 2021-08-04 12:45:18 -07:00
align.ll
…
alloca.ll [RISCV][NFC] Regenerate RISCV CodeGen tests 2020-12-09 19:42:49 +00:00
alu8.ll Revert "[RISCV] Use zexti32/sexti32 in srliw/sraiw isel patterns to improve usage of those instructions." 2021-06-27 10:33:43 -07:00
alu16.ll [RISCV] Use SLLI/SRLI instead of SLLIW/SRLIW for (srl (and X, 0xffff), C) custom isel on RV64. 2021-04-11 13:59:51 -07:00
alu32.ll [RISCV] Insert a sext_inreg when type legalizing i32 shl by constant on RV64. 2021-08-26 10:20:19 -07:00
alu64.ll [RISCV] Add isel pattern to match (i64 (sra (shl X, 32), C)) to SRAIW if C > 32. 2020-11-25 21:57:48 -08:00
analyze-branch.ll [RISCV][NFC] Regenerate RISCV CodeGen tests 2020-12-09 19:42:49 +00:00
arith-with-overflow.ll
…
atomic-cmpxchg-flag.ll
…
atomic-cmpxchg.ll [RISCV] Teach isel to select ADDW/SUBW/MULW/SLLIW when only the lower 32-bits are used. 2021-08-18 10:22:00 -07:00
atomic-fence.ll
…
atomic-load-store.ll [RISCV][NFC] Regenerate RISCV CodeGen tests 2020-12-09 19:42:49 +00:00
atomic-rmw.ll Revert "Allow rematerialization of virtual reg uses" 2021-09-24 10:26:11 -07:00
atomic-signext.ll Revert "Allow rematerialization of virtual reg uses" 2021-09-24 10:26:11 -07:00
attributes.ll [RISCV] Support Zfhmin extension 2021-11-06 01:41:02 +08:00
blockaddress.ll [RISCV] Fix inaccurate annotations on PseudoBRIND 2020-08-21 11:38:42 +01:00
branch-relaxation.ll [RISCV] Indirect branch generation in position independent code 2020-08-17 13:09:26 +01:00
branch.ll [RISCV] Add isel-patterns to optimize (a < 1) into blez (a <= 0) 2021-03-15 11:32:43 -07:00
bswap-ctlz-cttz-ctpop.ll [LegalizeTypes][RISCV][PowerPC] Expand CTLZ/CTTZ/CTPOP instead of promoting if they'll be expanded later. 2021-10-22 09:10:01 -07:00
byval.ll [RISCV] Reorder the vector register allocation order. 2021-10-19 09:30:13 +08:00
callee-saved-fpr32s.ll [RISCV][NFC] Regenerate Calling Convention Tests 2021-01-14 22:35:17 +00:00
callee-saved-fpr64s.ll [RISCV][NFC] Regenerate Calling Convention Tests 2021-01-14 22:35:17 +00:00
callee-saved-gprs.ll [RISCV][NFC] Regenerate Calling Convention Tests 2021-01-14 22:35:17 +00:00
calling-conv-half.ll [RISCV] Improve constant materialization for stores of i16 or i32 negative constants. 2021-08-18 10:25:12 -07:00
calling-conv-ilp32-ilp32f-common.ll [RISCV][NFC] Regenerate Calling Convention Tests 2021-01-14 22:35:17 +00:00
calling-conv-ilp32-ilp32f-ilp32d-common.ll [RISCV][NFC] Regenerate Calling Convention Tests 2021-01-14 22:35:17 +00:00
calling-conv-ilp32.ll [RISCV][NFC] Regenerate Calling Convention Tests 2021-01-14 22:35:17 +00:00
calling-conv-ilp32d.ll [RISCV][NFC] Regenerate Calling Convention Tests 2021-01-14 22:35:17 +00:00
calling-conv-ilp32f-ilp32d-common.ll [RISCV][NFC] Regenerate Calling Convention Tests 2021-01-14 22:35:17 +00:00
calling-conv-lp64-lp64f-common.ll [RISCV][NFC] Regenerate Calling Convention Tests 2021-01-14 22:35:17 +00:00
calling-conv-lp64-lp64f-lp64d-common.ll [RISCV] Teach isel to select ADDW/SUBW/MULW/SLLIW when only the lower 32-bits are used. 2021-08-18 10:22:00 -07:00
calling-conv-lp64.ll [RISCV][NFC] Regenerate Calling Convention Tests 2021-01-14 22:35:17 +00:00
calling-conv-rv32f-ilp32.ll [RISCV][NFC] Regenerate Calling Convention Tests 2021-01-14 22:35:17 +00:00
calling-conv-sext-zext.ll [RISCV] Don't print zext.b alias. 2021-01-05 10:41:08 -08:00
calling-conv-vector-float.ll [RISCV] Fix a crash when lowering split float arguments 2021-07-22 09:55:26 +01:00
calls.ll [RISCV] Reorder the vector register allocation order. 2021-10-19 09:30:13 +08:00
cmp-bool.ll [DAGCombiner] Rebuild (setcc x, y, ==) from (xor (xor x, y), 1) 2020-07-15 07:34:22 +00:00
codemodel-lowering.ll [RISCV] Fix inaccurate annotations on PseudoBRIND 2020-08-21 11:38:42 +01:00
compress-float.ll
…
compress-inline-asm.ll
…
compress.ll [RISCV] Add support for printing pcrel immediates as absolute addresses in llvm-objdump 2020-12-04 10:34:12 -08:00
copy-frameindex.mir [RISCV] Reorder the vector register allocation order. 2021-10-19 09:30:13 +08:00
copysign-casts.ll [RISCV] Insert a sext_inreg when type legalizing i32 shl by constant on RV64. 2021-08-26 10:20:19 -07:00
disable-tail-calls.ll
…
disjoint.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
div.ll [RISCV] Improve codegen for i32 udiv/urem by constant on RV64. 2021-11-12 14:49:10 -08:00
double-arith.ll [RISCV] Add rv32i/rv64i command lines to some floating point tests. NFC 2021-11-11 10:56:27 -08:00
double-bitmanip-dagcombines.ll [RISCV] Improve 64-bit integer materialization for some cases. 2021-04-01 09:12:52 -07:00
double-br-fcmp.ll [RISCV] Enable shrink wrap by default 2021-09-02 09:47:58 -05:00
double-calling-conv.ll [RISCV] Reorder the vector register allocation order. 2021-10-19 09:30:13 +08:00
double-convert.ll [RISCV] Add rv32i/rv64i command lines to some floating point tests. NFC 2021-11-11 10:56:27 -08:00
double-fcmp.ll [RISCV] Add rv32i/rv64i command lines to some floating point tests. NFC 2021-11-11 10:56:27 -08:00
double-frem.ll [RISCV] Promote f16 frem with Zfh. 2021-11-10 17:35:07 -08:00
double-imm.ll
…
double-intrinsics.ll [RISCV] Add rv32i/rv64i command lines to some floating point tests. NFC 2021-11-11 10:56:27 -08:00
double-isnan.ll [RISCV][LegalizeDAG] Expand SETO and SETUO comparisons. Teach LegalizeDAG to expand SETUO expansion when UNE isn't legal. 2020-12-10 09:15:52 -08:00
double-mem.ll [RISCV] Teach RISCVMatInt about cases where it can use LUI+SLLI to replace LUI+ADDI+SLLI for large constants. 2021-07-20 09:22:06 -07:00
double-previous-failure.ll [RISCV] Reorder the vector register allocation order. 2021-10-19 09:30:13 +08:00
double-select-fcmp.ll [RISCV] Optimize select_cc after fp compare expansion 2021-01-14 13:41:40 -08:00
double-stack-spill-restore.ll [RISCV] Enable shrink wrap by default 2021-09-02 09:47:58 -05:00
dwarf-eh.ll
…
elf-preemption.ll [RISCV] Prefer to lower MC_GlobalAddress operands to .Lfoo$local 2021-05-11 11:29:45 -07:00
exception-pointer-register.ll [RISCV][NFC] Regenerate RISCV CodeGen tests 2020-12-09 19:42:49 +00:00
fastcc-float.ll [RISCV] Fix a crash when lowering split float arguments 2021-07-22 09:55:26 +01:00
fastcc-int.ll [RISCV] Reorder the vector register allocation order. 2021-10-19 09:30:13 +08:00
fixups-diff.ll test: clean up some of the RISCV tests (NFC) 2021-06-17 09:51:09 -07:00
fixups-relax-diff.ll test: clean up some of the RISCV tests (NFC) 2021-06-17 09:51:09 -07:00
float-arith.ll [RISCV] Add rv32i/rv64i command lines to some floating point tests. NFC 2021-11-11 10:56:27 -08:00
float-bit-preserving-dagcombines.ll [RISCV] Improve 64-bit integer materialization for some cases. 2021-04-01 09:12:52 -07:00
float-bitmanip-dagcombines.ll
…
float-br-fcmp.ll [RISCV] Enable shrink wrap by default 2021-09-02 09:47:58 -05:00
float-convert.ll [RISCV] Add rv32i/rv64i command lines to some floating point tests. NFC 2021-11-11 10:56:27 -08:00
float-fcmp.ll [RISCV] Add rv32i/rv64i command lines to some floating point tests. NFC 2021-11-11 10:56:27 -08:00
float-frem.ll [RISCV] Add rv32i/rv64i command lines to some floating point tests. NFC 2021-11-11 10:56:27 -08:00
float-imm.ll
…
float-intrinsics.ll [RISCV] Fixed duplicate RUN line on float-intrinsics.ll. NFC 2021-11-12 16:27:36 -08:00
float-isnan.ll [RISCV][LegalizeDAG] Expand SETO and SETUO comparisons. Teach LegalizeDAG to expand SETUO expansion when UNE isn't legal. 2020-12-10 09:15:52 -08:00
float-mem.ll [RISCV] Teach RISCVMatInt about cases where it can use LUI+SLLI to replace LUI+ADDI+SLLI for large constants. 2021-07-20 09:22:06 -07:00
float-select-fcmp.ll [RISCV] Optimize select_cc after fp compare expansion 2021-01-14 13:41:40 -08:00
flt-rounds.ll
…
fold-addi-loadstore.ll [RISCV][test] Add explicit dso_local to definitions in ELF static relocation model tests 2020-12-30 15:28:11 -08:00
fp-imm.ll
…
fp16-promote.ll [RISCV] Use softPromoteHalf legalization for fp16 without Zfh rather than PromoteFloat. 2021-04-01 12:41:57 -07:00
fp128.ll [RISCV][NFC] Regenerate RISCV CodeGen tests 2020-12-09 19:42:49 +00:00
fpenv.ll [RISCV] Custom lowering of SET_ROUNDING 2021-04-22 15:04:55 +07:00
frame-info.ll [RISCV] Enable shrink wrap by default 2021-09-02 09:47:58 -05:00
frame.ll [RISCV][NFC] Regenerate RISCV CodeGen tests 2020-12-09 19:42:49 +00:00
frameaddr-returnaddr.ll [RISCV][NFC] Regenerate RISCV CodeGen tests 2020-12-09 19:42:49 +00:00
get-register-invalid.ll
…
get-register-noreserve.ll
…
get-register-reserve.ll
…
get-setcc-result-type.ll
…
ghccc-rv32.ll [RISCV][NFC] Regenerate RISCV CodeGen tests 2020-12-09 19:42:49 +00:00
ghccc-rv64.ll [RISCV][NFC] Regenerate RISCV CodeGen tests 2020-12-09 19:42:49 +00:00
half-arith.ll [RISCV] Add rv32i/rv64i command lines to some floating point tests. NFC 2021-11-11 10:56:27 -08:00
half-bitmanip-dagcombines.ll [RISCV] Add optimizations for FMV_X_ANYEXTH similar to FMV_X_ANYEXTW_RV64. 2021-08-08 18:30:48 -07:00
half-br-fcmp.ll [RISCV] Enable shrink wrap by default 2021-09-02 09:47:58 -05:00
half-convert.ll [RISCV] Add rv32i/rv64i command lines to some floating point tests. NFC 2021-11-11 10:56:27 -08:00
half-fcmp.ll [RISCV] Add rv32i/rv64i command lines to some floating point tests. NFC 2021-11-11 10:56:27 -08:00
half-frem.ll [RISCV] Promote f16 frem with Zfh. 2021-11-10 17:35:07 -08:00
half-imm.ll [RISCV] Support Zfh half-precision floating-point extension. 2020-12-03 09:16:33 +08:00
half-intrinsics.ll [RISCV] Add rv32i/rv64i command lines to some floating point tests. NFC 2021-11-11 10:56:27 -08:00
half-isnan.ll [RISCV][LegalizeDAG] Expand SETO and SETUO comparisons. Teach LegalizeDAG to expand SETUO expansion when UNE isn't legal. 2020-12-10 09:15:52 -08:00
half-mem.ll [RISCV] Teach RISCVMatInt about cases where it can use LUI+SLLI to replace LUI+ADDI+SLLI for large constants. 2021-07-20 09:22:06 -07:00
half-select-fcmp.ll [RISCV] Optimize select_cc after fp compare expansion 2021-01-14 13:41:40 -08:00
hoist-global-addr-base.ll [RISCV] Add riscv64 command line to hoist-global-addr-base.ll. NFC 2021-10-04 17:01:59 -07:00
i32-icmp.ll
…
imm-cse.ll
…
imm.ll [RISCV] Optimize immediate materialisation with SH*ADD 2021-11-15 23:34:28 +00:00
indirectbr.ll [RISCV] Fix inaccurate annotations on PseudoBRIND 2020-08-21 11:38:42 +01:00
init-array.ll
…
inline-asm-S-constraint.ll [RISCV] Support machine constraint "S" 2021-07-13 09:30:09 -07:00
inline-asm-abi-names.ll [RISCV][NFC] Regenerate RISCV CodeGen tests 2020-12-09 19:42:49 +00:00
inline-asm-clobbers.ll
…
inline-asm-d-abi-names.ll [RISCV][NFC] Regenerate RISCV CodeGen tests 2020-12-09 19:42:49 +00:00
inline-asm-d-constraint-f.ll
…
inline-asm-f-abi-names.ll [RISCV][NFC] Regenerate RISCV CodeGen tests 2020-12-09 19:42:49 +00:00
inline-asm-f-constraint-f.ll
…
inline-asm-i-constraint-i1.ll
…
inline-asm-invalid.ll
…
inline-asm.ll [MC][RISCV] Set UseIntegratedAssembler to true 2020-07-12 21:04:48 -07:00
interrupt-attr-args-error.ll
…
interrupt-attr-callee.ll [RISCV][NFC] Regenerate RISCV CodeGen tests 2020-12-09 19:42:49 +00:00
interrupt-attr-invalid.ll
…
interrupt-attr-nocall.ll [RISCV][NFC] Regenerate RISCV CodeGen tests 2020-12-09 19:42:49 +00:00
interrupt-attr-ret-error.ll
…
interrupt-attr.ll [RISCV][NFC] Regenerate RISCV CodeGen tests 2020-12-09 19:42:49 +00:00
jumptable.ll [CGP][RISCV] Teach CodeGenPrepare::optimizeSwitchInst to honor isSExtCheaperThanZExt. 2021-06-23 15:38:11 -07:00
large-stack.ll [RISCV] remove redundant instruction when eliminate frame index 2021-03-21 18:54:00 +08:00
legalize-fneg.ll
…
lit.local.cfg
…
live-sp.mir [RISCV] Fix invalid kill on callee save 2021-11-02 11:56:54 +00:00
lsr-legaladdimm.ll
…
machineoutliner-jumptable.mir [RISCV] Fix Machine Outliner jump table handling. 2021-09-09 07:32:30 +02:00
machineoutliner.mir
…
mattr-invalid-combination.ll
…
mem.ll [RISCV][test] Add explicit dso_local to definitions in ELF static relocation model tests 2020-12-30 15:28:11 -08:00
mem64.ll [RISCV][test] Add explicit dso_local to definitions in ELF static relocation model tests 2020-12-30 15:28:11 -08:00
mir-target-flags.ll [TargetMachine] Don't imply dso_local on function declarations in Reloc::Static model for ELF/wasm 2020-12-05 14:54:37 -08:00
module-target-abi.ll
…
module-target-abi2.ll
…
mul.ll Revert "Allow rematerialization of virtual reg uses" 2021-09-24 10:26:11 -07:00
musttail-call.ll OpaquePtr: Bulk update tests to use typed sret 2020-11-20 17:58:26 -05:00
neg-abs.ll [RISCV][NFC] Increase test coverage of Zbt extension 2021-01-18 17:30:35 +00:00
nomerge.ll
…
option-nopic.ll
…
option-norelax.ll
…
option-norvc.ll
…
option-pic.ll
…
option-relax.ll
…
option-rvc.ll
…
out-of-reach-emergency-slot.mir [RISCV][PrologEpilogInserter] "Float" emergency spill slots to avoid making them immediately unreachable from the stack pointer 2021-01-23 09:10:03 +00:00
overflow-intrinsic-optimizations.ll [RISCVISelLowering] avoid emitting libcalls to __mulodi4() and __multi3() 2021-08-31 11:23:56 -07:00
patchable-function-entry.ll Revert "[RISCV] Remove -riscv-no-aliases in favour of new -M no-aliases" 2021-05-29 15:11:37 +01:00
pic-models.ll Revert "[RISCV] Avoid Splitting MBB in RISCVExpandPseudo" 2020-07-14 11:15:01 +01:00
pr40333.ll
…
pr51206.ll [RISCV] Restrict performANY_EXTENDCombine to prevent an infinite loop. 2021-07-28 09:05:45 -07:00
prefetch.ll
…
readcyclecounter.ll
…
rem.ll [RISCV] Add custom isel to select (and (srl X, C1), C2) and (and (shl X, C1), C2) 2021-07-20 08:53:55 -07:00
remat.ll [RISCV][NFC] Regenerate RISCV CodeGen tests 2020-12-09 19:42:49 +00:00
reserved-reg-errors.ll
…
reserved-regs.ll
…
rotl-rotr.ll
…
rv32e.ll
…
rv32i-rv64i-float-double.ll [RISCV][NFC] Regenerate RISCV CodeGen tests 2020-12-09 19:42:49 +00:00
rv32i-rv64i-half.ll Revert "Allow rematerialization of virtual reg uses" 2021-09-24 10:26:11 -07:00
rv32zba.ll [RISCV] Remove experimental-b extension that includes all Zb* extensions 2021-10-07 20:47:17 -07:00
rv32zbb-intrinsic.ll [RISCV] Remove experimental-b extension that includes all Zb* extensions 2021-10-07 20:47:17 -07:00
rv32zbb-zbp.ll [SelectionDAG] Optimize expansion for rotates/funnel shifts 2021-11-02 11:38:25 +00:00
rv32zbb.ll [RISCV] Remove experimental-b extension that includes all Zb* extensions 2021-10-07 20:47:17 -07:00
rv32zbc-intrinsic.ll [RISCV] Remove experimental-b extension that includes all Zb* extensions 2021-10-07 20:47:17 -07:00
rv32zbe-intrinsic.ll [RISCV] Remove experimental-b extension that includes all Zb* extensions 2021-10-07 20:47:17 -07:00
rv32zbp-intrinsic.ll [RISCV] Remove experimental-b extension that includes all Zb* extensions 2021-10-07 20:47:17 -07:00
rv32zbp.ll [DAG] MatchRotate - support rotate-by-constant of illegal types 2021-11-19 11:12:04 +00:00
rv32zbr.ll [RISCV] Add IR intrinsic for Zbr extension 2021-04-02 10:58:45 -07:00
rv32zbs.ll [RISCV] Remove experimental-b extension that includes all Zb* extensions 2021-10-07 20:47:17 -07:00
rv32zbt.ll [SelectionDAG] Optimize expansion for rotates/funnel shifts 2021-11-02 11:38:25 +00:00
rv64-large-stack.ll [RISCV] Teach RISCVMatInt about cases where it can use LUI+SLLI to replace LUI+ADDI+SLLI for large constants. 2021-07-20 09:22:06 -07:00
rv64d-double-convert.ll [RISCV] Custom lower (i32 (fptoui/fptosi X)). 2021-07-24 10:50:43 -07:00
rv64f-float-convert.ll [RISCV] Custom lower (i32 (fptoui/fptosi X)). 2021-07-24 10:50:43 -07:00
rv64f-half-convert.ll [RISCV] Custom lower (i32 (fptoui/fptosi X)). 2021-07-24 10:50:43 -07:00
rv64i-complex-float.ll [RISCV][NFC] Regenerate RISCV CodeGen tests 2020-12-09 19:42:49 +00:00
rv64i-demanded-bits.ll [RISCV] Teach isel to select ADDW/SUBW/MULW/SLLIW when only the lower 32-bits are used. 2021-08-18 10:22:00 -07:00
rv64i-double-softfloat.ll [RISCV] Add rv32i/rv64i command lines to some floating point tests. NFC 2021-11-11 10:56:27 -08:00
rv64i-exhaustive-w-insts.ll [RISCV] Select (srl (sext_inreg X, i32), uimm5) to SRAIW if only lower 32 bits are used. 2021-09-16 11:03:35 -07:00
rv64i-single-softfloat.ll [RISCV] Add rv32i/rv64i command lines to some floating point tests. NFC 2021-11-11 10:56:27 -08:00
rv64i-tricky-shifts.ll
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rv64i-w-insts-legalization.ll [RISCV] Teach isel to select ADDW/SUBW/MULW/SLLIW when only the lower 32-bits are used. 2021-08-18 10:22:00 -07:00
rv64m-exhaustive-w-insts.ll [RISCV] Teach isel to select ADDW/SUBW/MULW/SLLIW when only the lower 32-bits are used. 2021-08-18 10:22:00 -07:00
rv64m-w-insts-legalization.ll Revert "[BPI] Improve static heuristics for integer comparisons" 2020-08-17 20:44:33 +02:00
rv64zba.ll [RISCV] Remove experimental-b extension that includes all Zb* extensions 2021-10-07 20:47:17 -07:00
rv64zbb-intrinsic.ll [RISCV] Remove experimental-b extension that includes all Zb* extensions 2021-10-07 20:47:17 -07:00
rv64zbb-zbp.ll [RISCV] Remove experimental-b extension that includes all Zb* extensions 2021-10-07 20:47:17 -07:00
rv64zbb.ll [LegalizeTypes][RISCV][PowerPC] Expand CTLZ/CTTZ/CTPOP instead of promoting if they'll be expanded later. 2021-10-22 09:10:01 -07:00
rv64zbc-intrinsic.ll [RISCV] Remove experimental-b extension that includes all Zb* extensions 2021-10-07 20:47:17 -07:00
rv64zbe-intrinsic.ll [RISCV] Remove experimental-b extension that includes all Zb* extensions 2021-10-07 20:47:17 -07:00
rv64zbp-intrinsic.ll [RISCV] Remove experimental-b extension that includes all Zb* extensions 2021-10-07 20:47:17 -07:00
rv64zbp.ll [DAG] MatchRotate - support rotate-by-constant of illegal types 2021-11-19 11:12:04 +00:00
rv64zbr.ll [RISCV] Add IR intrinsic for Zbr extension 2021-04-02 10:58:45 -07:00
rv64zbs.ll [RISCV] Remove experimental-b extension that includes all Zb* extensions 2021-10-07 20:47:17 -07:00
rv64zbt.ll [RISCV] Remove experimental-b extension that includes all Zb* extensions 2021-10-07 20:47:17 -07:00
sadd_sat.ll [ISel] Expand saddsat and ssubsat via asr and xor 2021-08-19 16:08:07 +01:00
sadd_sat_plus.ll [ISel] Expand saddsat and ssubsat via asr and xor 2021-08-19 16:08:07 +01:00
saverestore.ll [RISCV] Don't emit save-restore call if function is a interrupt handler 2021-04-16 12:54:47 +08:00
scalable-vector-struct.ll [RISCV] Use whole register load/store for generic load/store. 2021-02-09 15:52:04 +08:00
sdata-limit-0.ll
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sdata-limit-4.ll
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sdata-limit-8.ll
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sdata-local-sym.ll
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select-and.ll Recommit "[RISCV] Legalize select when Zbt extension available" 2021-01-21 12:07:44 -08:00
select-bare.ll Recommit "[RISCV] Legalize select when Zbt extension available" 2021-01-21 12:07:44 -08:00
select-binop-identity.ll [RISCV] Fold (add (select lhs, rhs, cc, 0, y), x) -> (select lhs, rhs, cc, x, (add x, y)) 2021-08-10 09:02:56 -07:00
select-cc.ll [RISCV] Support RISCVISD::SELECT_CC in ComputeNumSignBitsForTargetNode. 2021-08-13 18:00:09 -07:00
select-const.ll Recommit "[RISCV] Legalize select when Zbt extension available" 2021-01-21 12:07:44 -08:00
select-constant-xor.ll [NFC] Update test/CodeGen/RISCV/select-constant-xor.ll to use RV --check-prefix 2021-10-25 12:18:07 +05:30
select-optimize-multiple.ll [RISCV] Add more cmov isel patterns to handle seteq/ne with a small non-zero immediate. 2021-01-22 14:51:22 -08:00
select-optimize-multiple.mir [RISCV] Reorder the vector register allocation order. 2021-10-19 09:30:13 +08:00
select-or.ll Recommit "[RISCV] Legalize select when Zbt extension available" 2021-01-21 12:07:44 -08:00
selectcc-to-shiftand.ll [RISCV] Override TargetLowering::hasAndNot for Zbb. 2021-11-15 18:44:07 -08:00
setcc-logic.ll [RISCV] Insert sext_inreg when type legalizing add/sub/mul with constant LHS. 2021-08-18 10:44:25 -07:00
sext-zext-trunc.ll [TargetLowering][RISCV] Don't transform (seteq/ne (sext_inreg X, VT), C1) -> (seteq/ne (zext_inreg X, VT), C1) if the sext_inreg is cheaper 2021-01-25 16:37:21 -08:00
shadowcallstack.ll [RISCV] Teach isel to select ADDW/SUBW/MULW/SLLIW when only the lower 32-bits are used. 2021-08-18 10:22:00 -07:00
shift-and.ll [RISCV] Add another isel optimization for (and (shl x, c2), c1) 2021-09-23 14:18:07 -07:00
shift-masked-shamt.ll [RISCV] Teach isel to select ADDW/SUBW/MULW/SLLIW when only the lower 32-bits are used. 2021-08-18 10:22:00 -07:00
shifts.ll [SelectionDAG] Optimize expansion for rotates/funnel shifts 2021-11-02 11:38:25 +00:00
shlimm-addimm.ll [RISCV][test] Add tests of (add (shl r, c0), c1) 2021-10-14 14:53:03 +00:00
shrinkwrap.ll [RISCV] Improve shrink wrap test (NFC) 2021-09-02 12:14:04 -05:00
sink-icmp.ll [RISCV] Don't call setHasMultipleConditionRegisters(), so icmp is sunk 2021-11-19 08:32:59 -08:00
spill-fpr-scalar.ll [RISCV] Avoid using x0,x0 vsetvli for vmv.x.s and vfmv.f.s unless we know the sew/lmul ratio is constant. 2021-07-23 09:12:05 -07:00
split-offsets.ll [RISCV] Insert sext_inreg when type legalizing add/sub/mul with constant LHS. 2021-08-18 10:44:25 -07:00
split-sp-adjust.ll [RISCV][NFC] Regenerate RISCV CodeGen tests 2020-12-09 19:42:49 +00:00
srem-lkk.ll [RISCV] Select (srl (sext_inreg X, i32), uimm5) to SRAIW if only lower 32 bits are used. 2021-09-16 11:03:35 -07:00
srem-seteq-illegal-types.ll [DAG] MatchRotate - support rotate-by-constant of illegal types 2021-11-19 11:12:04 +00:00
srem-vector-lkk.ll Revert "Allow rematerialization of virtual reg uses" 2021-09-24 10:26:11 -07:00
ssub_sat.ll [ISel] Expand saddsat and ssubsat via asr and xor 2021-08-19 16:08:07 +01:00
ssub_sat_plus.ll [ISel] Expand saddsat and ssubsat via asr and xor 2021-08-19 16:08:07 +01:00
stack-realignment-with-variable-sized-objects.ll [RISCV] Add implementation of targetShrinkDemandedConstant to optimize AND immediates. 2021-01-15 11:14:14 -08:00
stack-realignment.ll [RISCV] remove redundant instruction when eliminate frame index 2021-03-21 18:54:00 +08:00
stack-slot-size.ll [RISCV] Fix stack slot for argument types (Bug 49500) 2021-04-29 09:10:48 +01:00
stack-store-check.ll RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
subtarget-features-std-ext.ll
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tail-calls.ll [RISCV] Prevent use of t0(aka x5) as rs1 for jalr instructions. 2021-07-13 09:46:21 -07:00
target-abi-invalid.ll
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target-abi-valid.ll
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thread-pointer.ll
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tls-models.ll [RISCV][NFC] Regenerate RISCV CodeGen tests 2020-12-09 19:42:49 +00:00
uadd_sat.ll [RISCV] Improve i32 UADDSAT/USUBSAT on RV64. 2021-03-16 07:44:06 -07:00
uadd_sat_plus.ll [RISCV] Teach isel to select ADDW/SUBW/MULW/SLLIW when only the lower 32-bits are used. 2021-08-18 10:22:00 -07:00
umulo-128-legalisation-lowering.ll [RISCVISelLowering] avoid emitting libcalls to __mulodi4() and __multi3() 2021-08-31 11:23:56 -07:00
unfold-masked-merge-scalar-variablemask.ll [RISCV] Override TargetLowering::hasAndNot for Zbb. 2021-11-15 18:44:07 -08:00
urem-lkk.ll [RISCV] Improve codegen for i32 udiv/urem by constant on RV64. 2021-11-12 14:49:10 -08:00
urem-seteq-illegal-types.ll [SelectionDAG] Merge FoldConstantVectorArithmetic into FoldConstantArithmetic (PR36544) 2021-11-09 11:31:01 +00:00
urem-vector-lkk.ll Revert "Allow rematerialization of virtual reg uses" 2021-09-24 10:26:11 -07:00
usub_sat.ll [RISCV] Improve i32 UADDSAT/USUBSAT on RV64. 2021-03-16 07:44:06 -07:00
usub_sat_plus.ll [RISCV] Teach isel to select ADDW/SUBW/MULW/SLLIW when only the lower 32-bits are used. 2021-08-18 10:22:00 -07:00
vararg.ll [RISCV] Insert sext_inreg when type legalizing add/sub/mul with constant LHS. 2021-08-18 10:44:25 -07:00
vec3-setcc-crash.ll Revert "[RISCV] Use zexti32/sexti32 in srliw/sraiw isel patterns to improve usage of those instructions." 2021-06-27 10:33:43 -07:00
vector-abi.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
verify-instr.mir
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wide-mem.ll
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xaluo.ll [RISCVISelLowering] avoid emitting libcalls to __mulodi4() and __multi3() 2021-08-31 11:23:56 -07:00
zext-with-load-is-free.ll [RISCV][test] Add explicit dso_local to definitions in ELF static relocation model tests 2020-12-30 15:28:11 -08:00
zfh-imm.ll [RISCV] Support Zfh half-precision floating-point extension. 2020-12-03 09:16:33 +08:00