forked from OSchip/llvm-project
101 lines
4.5 KiB
TableGen
101 lines
4.5 KiB
TableGen
// WebAssemblyInstrMemory.td-WebAssembly Memory codegen support -*- tablegen -*-
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// \brief WebAssembly Memory operand code-gen constructs.
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///
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//===----------------------------------------------------------------------===//
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/*
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* TODO(jfb): Add the following.
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*
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* load_global: load the value of a given global variable
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* store_global: store a given value to a given global variable
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*/
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// FIXME:
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// - HasAddr64
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// - WebAssemblyTargetLowering::isLegalAddressingMode
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// - WebAssemblyTargetLowering having to do with atomics
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// - Each has optional alignment and immediate byte offset.
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// WebAssembly has i8/i16/i32/i64/f32/f64 memory types, but doesn't have i8/i16
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// local types. These memory-only types instead zero- or sign-extend into local
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// types when loading, and truncate when storing.
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// Basic load.
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def LOAD_I32_ : I<(outs I32:$dst), (ins I32:$addr),
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[(set I32:$dst, (load I32:$addr))]>;
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def LOAD_I64_ : I<(outs I64:$dst), (ins I32:$addr),
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[(set I64:$dst, (load I32:$addr))]>;
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def LOAD_F32_ : I<(outs F32:$dst), (ins I32:$addr),
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[(set F32:$dst, (load I32:$addr))]>;
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def LOAD_F64_ : I<(outs F64:$dst), (ins I32:$addr),
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[(set F64:$dst, (load I32:$addr))]>;
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// Extending load.
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def LOAD_S_i8_I32_ : I<(outs I32:$dst), (ins I32:$addr),
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[(set I32:$dst, (sextloadi8 I32:$addr))]>;
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def LOAD_U_i8_I32_ : I<(outs I32:$dst), (ins I32:$addr),
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[(set I32:$dst, (zextloadi8 I32:$addr))]>;
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def LOAD_S_i16_I32_ : I<(outs I32:$dst), (ins I32:$addr),
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[(set I32:$dst, (sextloadi16 I32:$addr))]>;
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def LOAD_U_i16_I32_ : I<(outs I32:$dst), (ins I32:$addr),
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[(set I32:$dst, (zextloadi16 I32:$addr))]>;
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def LOAD_S_i8_I64_ : I<(outs I64:$dst), (ins I32:$addr),
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[(set I64:$dst, (sextloadi8 I32:$addr))]>;
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def LOAD_U_i8_I64_ : I<(outs I64:$dst), (ins I32:$addr),
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[(set I64:$dst, (zextloadi8 I32:$addr))]>;
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def LOAD_S_i16_I64_ : I<(outs I64:$dst), (ins I32:$addr),
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[(set I64:$dst, (sextloadi16 I32:$addr))]>;
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def LOAD_U_i16_I64_ : I<(outs I64:$dst), (ins I32:$addr),
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[(set I64:$dst, (zextloadi16 I32:$addr))]>;
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def LOAD_S_I32_I64_ : I<(outs I64:$dst), (ins I32:$addr),
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[(set I64:$dst, (sextloadi32 I32:$addr))]>;
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def LOAD_U_I32_I64_ : I<(outs I64:$dst), (ins I32:$addr),
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[(set I64:$dst, (zextloadi32 I32:$addr))]>;
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// "Don't care" extending load become zero-extending load.
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def : Pat<(i32 (extloadi8 I32:$addr)), (LOAD_U_i8_I32_ $addr)>;
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def : Pat<(i32 (extloadi16 I32:$addr)), (LOAD_U_i16_I32_ $addr)>;
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def : Pat<(i64 (extloadi8 I32:$addr)), (LOAD_U_i8_I64_ $addr)>;
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def : Pat<(i64 (extloadi16 I32:$addr)), (LOAD_U_i16_I64_ $addr)>;
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def : Pat<(i64 (extloadi32 I32:$addr)), (LOAD_U_I32_I64_ $addr)>;
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// Basic store.
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// Note: WebAssembly inverts SelectionDAG's usual operand order.
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def STORE_I32_ : I<(outs), (ins I32:$addr, I32:$val),
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[(store i32:$val, I32:$addr)]>;
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def STORE_I64_ : I<(outs), (ins I32:$addr, I64:$val),
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[(store i64:$val, I32:$addr)]>;
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def STORE_F32_ : I<(outs), (ins I32:$addr, F32:$val),
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[(store f32:$val, I32:$addr)]>;
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def STORE_F64_ : I<(outs), (ins I32:$addr, F64:$val),
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[(store f64:$val, I32:$addr)]>;
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// Truncating store.
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def STORE_i8_I32 : I<(outs), (ins I32:$addr, I32:$val),
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[(truncstorei8 I32:$val, I32:$addr)]>;
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def STORE_i16_I32 : I<(outs), (ins I32:$addr, I32:$val),
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[(truncstorei16 I32:$val, I32:$addr)]>;
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def STORE_i8_I64 : I<(outs), (ins I32:$addr, I64:$val),
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[(truncstorei8 I64:$val, I32:$addr)]>;
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def STORE_i16_I64 : I<(outs), (ins I32:$addr, I64:$val),
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[(truncstorei16 I64:$val, I32:$addr)]>;
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def STORE_I32_I64 : I<(outs), (ins I32:$addr, I64:$val),
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[(truncstorei32 I64:$val, I32:$addr)]>;
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// Page size.
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def page_size_I32 : I<(outs I32:$dst), (ins),
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[(set I32:$dst, (int_wasm_page_size))]>,
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Requires<[HasAddr32]>;
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def page_size_I64 : I<(outs I64:$dst), (ins),
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[(set I64:$dst, (int_wasm_page_size))]>,
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Requires<[HasAddr64]>;
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