forked from OSchip/llvm-project
218 lines
5.6 KiB
LLVM
218 lines
5.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -instcombine -S | FileCheck %s
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define i32 @test1(i32 %X, i8 %A) {
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; CHECK-LABEL: @test1(
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; CHECK-NEXT: [[SHIFT_UPGRD_1:%.*]] = zext i8 %A to i32
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; CHECK-NEXT: [[Y1:%.*]] = lshr i32 %X, [[SHIFT_UPGRD_1]]
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; CHECK-NEXT: [[Z:%.*]] = and i32 [[Y1]], 1
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; CHECK-NEXT: ret i32 [[Z]]
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;
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%shift.upgrd.1 = zext i8 %A to i32
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; can be logical shift.
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%Y = ashr i32 %X, %shift.upgrd.1
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%Z = and i32 %Y, 1
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ret i32 %Z
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}
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define i32 @test2(i8 %tmp) {
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; CHECK-LABEL: @test2(
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; CHECK-NEXT: [[TMP3:%.*]] = zext i8 %tmp to i32
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; CHECK-NEXT: [[TMP4:%.*]] = add nuw nsw i32 [[TMP3]], 7
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; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[TMP4]], 3
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; CHECK-NEXT: ret i32 [[TMP1]]
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;
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%tmp3 = zext i8 %tmp to i32
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%tmp4 = add i32 %tmp3, 7
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%tmp5 = ashr i32 %tmp4, 3
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ret i32 %tmp5
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}
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define i64 @test3(i1 %X, i64 %Y, i1 %Cond) {
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; CHECK-LABEL: @test3(
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; CHECK-NEXT: br i1 %Cond, label %T, label %F
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; CHECK: T:
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; CHECK-NEXT: [[X2:%.*]] = sext i1 %X to i64
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; CHECK-NEXT: br label %C
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; CHECK: F:
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; CHECK-NEXT: [[Y2:%.*]] = ashr i64 %Y, 63
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; CHECK-NEXT: br label %C
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; CHECK: C:
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; CHECK-NEXT: [[P:%.*]] = phi i64 [ [[X2]], %T ], [ [[Y2]], %F ]
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; CHECK-NEXT: ret i64 [[P]]
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;
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br i1 %Cond, label %T, label %F
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T:
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%X2 = sext i1 %X to i64
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br label %C
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F:
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%Y2 = ashr i64 %Y, 63
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br label %C
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C:
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%P = phi i64 [%X2, %T], [%Y2, %F]
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%S = ashr i64 %P, 12
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ret i64 %S
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}
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define i64 @test4(i1 %X, i64 %Y, i1 %Cond) {
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; CHECK-LABEL: @test4(
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; CHECK-NEXT: br i1 %Cond, label %T, label %F
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; CHECK: T:
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; CHECK-NEXT: [[X2:%.*]] = sext i1 %X to i64
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; CHECK-NEXT: br label %C
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; CHECK: F:
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; CHECK-NEXT: [[Y2:%.*]] = ashr i64 %Y, 63
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; CHECK-NEXT: br label %C
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; CHECK: C:
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; CHECK-NEXT: [[P:%.*]] = phi i64 [ [[X2]], %T ], [ [[Y2]], %F ]
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; CHECK-NEXT: ret i64 [[P]]
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;
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br i1 %Cond, label %T, label %F
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T:
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%X2 = sext i1 %X to i64
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br label %C
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F:
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%Y2 = ashr i64 %Y, 63
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br label %C
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C:
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%P = phi i64 [%X2, %T], [%Y2, %F]
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%R = shl i64 %P, 12
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%S = ashr i64 %R, 12
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ret i64 %S
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}
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; rdar://7732987
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define i32 @test5(i32 %Y) {
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; CHECK-LABEL: @test5(
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; CHECK-NEXT: br i1 undef, label %A, label %C
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; CHECK: A:
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; CHECK-NEXT: br i1 undef, label %B, label %D
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; CHECK: B:
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; CHECK-NEXT: br label %D
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; CHECK: C:
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; CHECK-NEXT: br i1 undef, label %D, label %E
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; CHECK: D:
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; CHECK-NEXT: [[P:%.*]] = phi i32 [ 0, %A ], [ 0, %B ], [ %Y, %C ]
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; CHECK-NEXT: [[S:%.*]] = ashr i32 [[P]], 16
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; CHECK-NEXT: ret i32 [[S]]
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; CHECK: E:
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; CHECK-NEXT: ret i32 0
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;
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br i1 undef, label %A, label %C
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A:
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br i1 undef, label %B, label %D
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B:
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br label %D
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C:
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br i1 undef, label %D, label %E
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D:
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%P = phi i32 [0, %A], [0, %B], [%Y, %C]
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%S = ashr i32 %P, 16
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ret i32 %S
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E:
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ret i32 0
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}
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; (X >>s C1) >>s C2 --> X >>s (C1 + C2)
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define i32 @ashr_ashr(i32 %x) {
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; CHECK-LABEL: @ashr_ashr(
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; CHECK-NEXT: [[SH2:%.*]] = ashr i32 %x, 12
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; CHECK-NEXT: ret i32 [[SH2]]
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;
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%sh1 = ashr i32 %x, 5
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%sh2 = ashr i32 %sh1, 7
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ret i32 %sh2
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}
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; PR3851
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; (X >>s C1) >>s C2 --> X >>s (Bitwidth - 1)
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define i32 @ashr_overshift(i32 %x) {
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; CHECK-LABEL: @ashr_overshift(
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; CHECK-NEXT: [[SH2:%.*]] = ashr i32 %x, 31
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; CHECK-NEXT: ret i32 [[SH2]]
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;
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%sh1 = ashr i32 %x, 15
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%sh2 = ashr i32 %sh1, 17
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ret i32 %sh2
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}
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; (X >>s C1) >>s C2 --> X >>s (C1 + C2)
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define <2 x i32> @ashr_ashr_splat_vec(<2 x i32> %x) {
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; CHECK-LABEL: @ashr_ashr_splat_vec(
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; CHECK-NEXT: [[SH2:%.*]] = ashr <2 x i32> %x, <i32 12, i32 12>
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; CHECK-NEXT: ret <2 x i32> [[SH2]]
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;
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%sh1 = ashr <2 x i32> %x, <i32 5, i32 5>
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%sh2 = ashr <2 x i32> %sh1, <i32 7, i32 7>
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ret <2 x i32> %sh2
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}
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; (X >>s C1) >>s C2 --> X >>s (Bitwidth - 1)
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define <2 x i32> @ashr_overshift_splat_vec(<2 x i32> %x) {
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; CHECK-LABEL: @ashr_overshift_splat_vec(
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; CHECK-NEXT: [[SH2:%.*]] = ashr <2 x i32> %x, <i32 31, i32 31>
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; CHECK-NEXT: ret <2 x i32> [[SH2]]
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;
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%sh1 = ashr <2 x i32> %x, <i32 15, i32 15>
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%sh2 = ashr <2 x i32> %sh1, <i32 17, i32 17>
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ret <2 x i32> %sh2
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}
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; ashr (sext X), C --> sext (ashr X, C')
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define i32 @hoist_ashr_ahead_of_sext_1(i8 %x) {
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; CHECK-LABEL: @hoist_ashr_ahead_of_sext_1(
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; CHECK-NEXT: [[TMP1:%.*]] = ashr i8 %x, 3
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; CHECK-NEXT: [[R:%.*]] = sext i8 [[TMP1]] to i32
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; CHECK-NEXT: ret i32 [[R]]
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;
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%sext = sext i8 %x to i32
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%r = ashr i32 %sext, 3
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ret i32 %r
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}
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; ashr (sext X), C --> sext (ashr X, C')
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define <2 x i32> @hoist_ashr_ahead_of_sext_1_splat(<2 x i8> %x) {
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; CHECK-LABEL: @hoist_ashr_ahead_of_sext_1_splat(
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; CHECK-NEXT: [[TMP1:%.*]] = ashr <2 x i8> %x, <i8 3, i8 3>
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; CHECK-NEXT: [[R:%.*]] = sext <2 x i8> [[TMP1]] to <2 x i32>
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; CHECK-NEXT: ret <2 x i32> [[R]]
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;
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%sext = sext <2 x i8> %x to <2 x i32>
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%r = ashr <2 x i32> %sext, <i32 3, i32 3>
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ret <2 x i32> %r
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}
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; ashr (sext X), C --> sext (ashr X, C') -- the shift amount must be clamped
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define i32 @hoist_ashr_ahead_of_sext_2(i8 %x) {
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; CHECK-LABEL: @hoist_ashr_ahead_of_sext_2(
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; CHECK-NEXT: [[TMP1:%.*]] = ashr i8 %x, 7
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; CHECK-NEXT: [[R:%.*]] = sext i8 [[TMP1]] to i32
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; CHECK-NEXT: ret i32 [[R]]
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;
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%sext = sext i8 %x to i32
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%r = ashr i32 %sext, 8
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ret i32 %r
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}
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; ashr (sext X), C --> sext (ashr X, C') -- the shift amount must be clamped
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define <2 x i32> @hoist_ashr_ahead_of_sext_2_splat(<2 x i8> %x) {
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; CHECK-LABEL: @hoist_ashr_ahead_of_sext_2_splat(
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; CHECK-NEXT: [[TMP1:%.*]] = ashr <2 x i8> %x, <i8 7, i8 7>
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; CHECK-NEXT: [[R:%.*]] = sext <2 x i8> [[TMP1]] to <2 x i32>
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; CHECK-NEXT: ret <2 x i32> [[R]]
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;
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%sext = sext <2 x i8> %x to <2 x i32>
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%r = ashr <2 x i32> %sext, <i32 8, i32 8>
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ret <2 x i32> %r
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}
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