forked from OSchip/llvm-project
880 lines
26 KiB
LLVM
880 lines
26 KiB
LLVM
; RUN: opt -instcombine -S -o - %s | FileCheck %s
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define i1 @masked_and_notallzeroes(i32 %A) {
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; CHECK-LABEL: @masked_and_notallzeroes(
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; CHECK-NEXT: [[MASK1:%.*]] = and i32 %A, 7
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; CHECK-NEXT: [[TST1:%.*]] = icmp ne i32 [[MASK1]], 0
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; CHECK-NEXT: ret i1 [[TST1]]
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;
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%mask1 = and i32 %A, 7
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%tst1 = icmp ne i32 %mask1, 0
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%mask2 = and i32 %A, 39
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%tst2 = icmp ne i32 %mask2, 0
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%res = and i1 %tst1, %tst2
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ret i1 %res
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}
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define i1 @masked_or_allzeroes(i32 %A) {
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; CHECK-LABEL: @masked_or_allzeroes(
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; CHECK-NEXT: [[MASK1:%.*]] = and i32 %A, 7
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; CHECK-NEXT: [[TST1:%.*]] = icmp eq i32 [[MASK1]], 0
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; CHECK-NEXT: ret i1 [[TST1]]
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;
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%mask1 = and i32 %A, 7
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%tst1 = icmp eq i32 %mask1, 0
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%mask2 = and i32 %A, 39
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%tst2 = icmp eq i32 %mask2, 0
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%res = or i1 %tst1, %tst2
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ret i1 %res
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}
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define i1 @masked_and_notallones(i32 %A) {
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; CHECK-LABEL: @masked_and_notallones(
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; CHECK-NEXT: [[MASK1:%.*]] = and i32 %A, 7
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; CHECK-NEXT: [[TST1:%.*]] = icmp ne i32 [[MASK1]], 7
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; CHECK-NEXT: ret i1 [[TST1]]
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;
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%mask1 = and i32 %A, 7
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%tst1 = icmp ne i32 %mask1, 7
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%mask2 = and i32 %A, 39
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%tst2 = icmp ne i32 %mask2, 39
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%res = and i1 %tst1, %tst2
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ret i1 %res
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}
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define i1 @masked_or_allones(i32 %A) {
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; CHECK-LABEL: @masked_or_allones(
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; CHECK-NEXT: [[MASK1:%.*]] = and i32 %A, 7
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; CHECK-NEXT: [[TST1:%.*]] = icmp eq i32 [[MASK1]], 7
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; CHECK-NEXT: ret i1 [[TST1]]
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;
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%mask1 = and i32 %A, 7
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%tst1 = icmp eq i32 %mask1, 7
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%mask2 = and i32 %A, 39
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%tst2 = icmp eq i32 %mask2, 39
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%res = or i1 %tst1, %tst2
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ret i1 %res
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}
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define i1 @masked_and_notA(i32 %A) {
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; CHECK-LABEL: @masked_and_notA(
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; CHECK-NEXT: [[MASK2:%.*]] = and i32 %A, 39
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; CHECK-NEXT: [[TST2:%.*]] = icmp ne i32 [[MASK2]], %A
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; CHECK-NEXT: ret i1 [[TST2]]
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;
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%mask1 = and i32 %A, 7
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%tst1 = icmp ne i32 %mask1, %A
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%mask2 = and i32 %A, 39
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%tst2 = icmp ne i32 %mask2, %A
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%res = and i1 %tst1, %tst2
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ret i1 %res
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}
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define i1 @masked_or_A(i32 %A) {
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; CHECK-LABEL: @masked_or_A(
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; CHECK-NEXT: [[MASK2:%.*]] = and i32 %A, 39
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; CHECK-NEXT: [[TST2:%.*]] = icmp eq i32 [[MASK2]], %A
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; CHECK-NEXT: ret i1 [[TST2]]
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;
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%mask1 = and i32 %A, 7
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%tst1 = icmp eq i32 %mask1, %A
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%mask2 = and i32 %A, 39
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%tst2 = icmp eq i32 %mask2, %A
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%res = or i1 %tst1, %tst2
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ret i1 %res
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}
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define i1 @masked_or_allzeroes_notoptimised(i32 %A) {
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; CHECK-LABEL: @masked_or_allzeroes_notoptimised(
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; CHECK-NEXT: [[MASK1:%.*]] = and i32 %A, 15
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; CHECK-NEXT: [[TST1:%.*]] = icmp eq i32 [[MASK1]], 0
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; CHECK-NEXT: [[MASK2:%.*]] = and i32 %A, 39
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; CHECK-NEXT: [[TST2:%.*]] = icmp eq i32 [[MASK2]], 0
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; CHECK-NEXT: [[RES:%.*]] = or i1 [[TST1]], [[TST2]]
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; CHECK-NEXT: ret i1 [[RES]]
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;
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%mask1 = and i32 %A, 15
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%tst1 = icmp eq i32 %mask1, 0
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%mask2 = and i32 %A, 39
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%tst2 = icmp eq i32 %mask2, 0
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%res = or i1 %tst1, %tst2
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ret i1 %res
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}
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define i1 @nomask_lhs(i32 %in) {
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; CHECK-LABEL: @nomask_lhs(
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; CHECK-NEXT: [[MASKED:%.*]] = and i32 %in, 1
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; CHECK-NEXT: [[TST2:%.*]] = icmp eq i32 [[MASKED]], 0
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; CHECK-NEXT: ret i1 [[TST2]]
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;
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%tst1 = icmp eq i32 %in, 0
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%masked = and i32 %in, 1
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%tst2 = icmp eq i32 %masked, 0
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%val = or i1 %tst1, %tst2
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ret i1 %val
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}
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define i1 @nomask_rhs(i32 %in) {
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; CHECK-LABEL: @nomask_rhs(
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; CHECK-NEXT: [[MASKED:%.*]] = and i32 %in, 1
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; CHECK-NEXT: [[TST1:%.*]] = icmp eq i32 [[MASKED]], 0
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; CHECK-NEXT: ret i1 [[TST1]]
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;
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%masked = and i32 %in, 1
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%tst1 = icmp eq i32 %masked, 0
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%tst2 = icmp eq i32 %in, 0
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%val = or i1 %tst1, %tst2
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ret i1 %val
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}
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; TODO: This test simplifies to a constant, so the functionality and test could be in InstSimplify.
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define i1 @fold_mask_cmps_to_false(i32 %x) {
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; CHECK-LABEL: @fold_mask_cmps_to_false(
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; CHECK-NEXT: ret i1 false
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;
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%1 = and i32 %x, 2147483647
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%2 = icmp eq i32 %1, 0
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%3 = icmp eq i32 %x, 2147483647
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%4 = and i1 %3, %2
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ret i1 %4
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}
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; TODO: This test simplifies to a constant, so the functionality and test could be in InstSimplify.
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define i1 @fold_mask_cmps_to_true(i32 %x) {
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; CHECK-LABEL: @fold_mask_cmps_to_true(
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; CHECK-NEXT: ret i1 true
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;
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%1 = and i32 %x, 2147483647
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%2 = icmp ne i32 %1, 0
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%3 = icmp ne i32 %x, 2147483647
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%4 = or i1 %3, %2
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ret i1 %4
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}
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; PR32401 - https://bugs.llvm.org/show_bug.cgi?id=32401
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define i1 @cmpeq_bitwise(i8 %a, i8 %b, i8 %c, i8 %d) {
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; CHECK-LABEL: @cmpeq_bitwise(
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; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i8 %a, %b
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; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i8 %c, %d
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; CHECK-NEXT: [[CMP:%.*]] = and i1 [[TMP1]], [[TMP2]]
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; CHECK-NEXT: ret i1 [[CMP]]
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;
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%xor1 = xor i8 %a, %b
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%xor2 = xor i8 %c, %d
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%or = or i8 %xor1, %xor2
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%cmp = icmp eq i8 %or, 0
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ret i1 %cmp
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}
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define <2 x i1> @cmpne_bitwise(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c, <2 x i64> %d) {
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; CHECK-LABEL: @cmpne_bitwise(
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; CHECK-NEXT: [[TMP1:%.*]] = icmp ne <2 x i64> %a, %b
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; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <2 x i64> %c, %d
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; CHECK-NEXT: [[CMP:%.*]] = or <2 x i1> [[TMP1]], [[TMP2]]
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; CHECK-NEXT: ret <2 x i1> [[CMP]]
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;
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%xor1 = xor <2 x i64> %a, %b
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%xor2 = xor <2 x i64> %c, %d
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%or = or <2 x i64> %xor1, %xor2
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%cmp = icmp ne <2 x i64> %or, zeroinitializer
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ret <2 x i1> %cmp
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}
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; ((X & 12) != 0 & (X & 3) == 1) -> no change
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define i1 @masked_icmps_mask_notallzeros_bmask_mixed_0(i32 %x) {
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; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_0(
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; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 12
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; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i32 [[AND1]], 0
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; CHECK-NEXT: [[AND2:%.*]] = and i32 %x, 3
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; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i32 [[AND2]], 1
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; CHECK-NEXT: [[AND3:%.*]] = and i1 [[CMP1]], [[CMP2]]
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; CHECK-NEXT: ret i1 [[AND3]]
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;
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%1 = and i32 %x, 12
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%2 = icmp ne i32 %1, 0
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%3 = and i32 %x, 3
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%4 = icmp eq i32 %3, 1
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%5 = and i1 %2, %4
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ret i1 %5
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}
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; ((X & 12) != 0 & (X & 7) == 1) -> (X & 15) == 9
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define i1 @masked_icmps_mask_notallzeros_bmask_mixed_1(i32 %x) {
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; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_1(
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; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 15
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; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[AND1]], 9
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; CHECK-NEXT: ret i1 [[CMP1]]
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;
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%1 = and i32 %x, 12
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%2 = icmp ne i32 %1, 0
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%3 = and i32 %x, 7
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%4 = icmp eq i32 %3, 1
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%5 = and i1 %2, %4
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ret i1 %5
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}
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; ((X & 14) != 0 & (X & 3) == 1) -> no change
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define i1 @masked_icmps_mask_notallzeros_bmask_mixed_1b(i32 %x) {
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; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_1b(
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; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 14
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; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i32 [[AND1]], 0
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; CHECK-NEXT: [[AND2:%.*]] = and i32 %x, 3
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; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i32 [[AND2]], 1
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; CHECK-NEXT: [[AND3:%.*]] = and i1 [[CMP1]], [[CMP2]]
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; CHECK-NEXT: ret i1 [[AND3]]
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;
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%1 = and i32 %x, 14
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%2 = icmp ne i32 %1, 0
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%3 = and i32 %x, 3
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%4 = icmp eq i32 %3, 1
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%5 = and i1 %2, %4
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ret i1 %5
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}
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; ((X & 3) != 0 & (X & 7) == 0) -> false
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define i1 @masked_icmps_mask_notallzeros_bmask_mixed_2(i32 %x) {
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; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_2(
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; CHECK-NEXT: ret i1 false
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;
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%1 = and i32 %x, 3
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%2 = icmp ne i32 %1, 0
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%3 = and i32 %x, 7
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%4 = icmp eq i32 %3, 0
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%5 = and i1 %2, %4
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ret i1 %5
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}
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; ((X & 15) != 0 & (X & 7) == 0) -> (X & 15) == 8
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define i1 @masked_icmps_mask_notallzeros_bmask_mixed_3(i32 %x) {
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; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_3(
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; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 15
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; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[AND1]], 8
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; CHECK-NEXT: ret i1 [[CMP1]]
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;
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%1 = and i32 %x, 15
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%2 = icmp ne i32 %1, 0
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%3 = and i32 %x, 7
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%4 = icmp eq i32 %3, 0
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%5 = and i1 %2, %4
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ret i1 %5
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}
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; ((X & 15) != 0 & (X & 3) == 0) -> no change
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define i1 @masked_icmps_mask_notallzeros_bmask_mixed_3b(i32 %x) {
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; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_3b(
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; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 15
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; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i32 [[AND1]], 0
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; CHECK-NEXT: [[AND2:%.*]] = and i32 %x, 3
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; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i32 [[AND2]], 0
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; CHECK-NEXT: [[AND3:%.*]] = and i1 [[CMP1]], [[CMP2]]
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; CHECK-NEXT: ret i1 [[AND3]]
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;
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%1 = and i32 %x, 15
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%2 = icmp ne i32 %1, 0
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%3 = and i32 %x, 3
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%4 = icmp eq i32 %3, 0
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%5 = and i1 %2, %4
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ret i1 %5
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}
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; ((X & 255) != 0 & (X & 15) == 8) -> (X & 15) == 8
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define i1 @masked_icmps_mask_notallzeros_bmask_mixed_4(i32 %x) {
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; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_4(
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; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 15
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; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[AND1]], 8
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; CHECK-NEXT: ret i1 [[CMP1]]
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;
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%1 = and i32 %x, 255
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%2 = icmp ne i32 %1, 0
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%3 = and i32 %x, 15
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%4 = icmp eq i32 %3, 8
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%5 = and i1 %2, %4
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ret i1 %5
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}
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; ((X & 15) != 0 & (X & 15) == 8) -> (X & 15) == 8
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define i1 @masked_icmps_mask_notallzeros_bmask_mixed_5(i32 %x) {
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; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_5(
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; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 15
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; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[AND1]], 8
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; CHECK-NEXT: ret i1 [[CMP1]]
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;
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%1 = and i32 %x, 15
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%2 = icmp ne i32 %1, 0
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%3 = and i32 %x, 15
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%4 = icmp eq i32 %3, 8
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%5 = and i1 %2, %4
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ret i1 %5
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}
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; ((X & 12) != 0 & (X & 15) == 8) -> (X & 15) == 8
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define i1 @masked_icmps_mask_notallzeros_bmask_mixed_6(i32 %x) {
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; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_6(
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; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 15
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; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[AND1]], 8
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; CHECK-NEXT: ret i1 [[CMP1]]
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;
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%1 = and i32 %x, 12
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%2 = icmp ne i32 %1, 0
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%3 = and i32 %x, 15
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%4 = icmp eq i32 %3, 8
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%5 = and i1 %2, %4
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ret i1 %5
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}
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; ((X & 7) != 0 & (X & 15) == 8) -> false
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define i1 @masked_icmps_mask_notallzeros_bmask_mixed_7(i32 %x) {
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; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_7(
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; CHECK-NEXT: ret i1 false
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;
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%1 = and i32 %x, 7
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%2 = icmp ne i32 %1, 0
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%3 = and i32 %x, 15
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%4 = icmp eq i32 %3, 8
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%5 = and i1 %2, %4
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ret i1 %5
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}
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; ((X & 6) != 0 & (X & 15) == 8) -> false
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define i1 @masked_icmps_mask_notallzeros_bmask_mixed_7b(i32 %x) {
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; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_7b(
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; CHECK-NEXT: ret i1 false
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;
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%1 = and i32 %x, 6
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%2 = icmp ne i32 %1, 0
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%3 = and i32 %x, 15
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%4 = icmp eq i32 %3, 8
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%5 = and i1 %2, %4
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ret i1 %5
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}
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; ((X & 12) == 0 | (X & 3) != 1) -> !((X & 12) != 0 & (X & 3) == 1)) ->
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; no change
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define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_0(i32 %x) {
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; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_0(
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; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 12
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; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[AND1]], 0
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; CHECK-NEXT: [[AND2:%.*]] = and i32 %x, 3
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; CHECK-NEXT: [[CMP2:%.*]] = icmp ne i32 [[AND2]], 1
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; CHECK-NEXT: [[OR1:%.*]] = or i1 [[CMP1]], [[CMP2]]
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; CHECK-NEXT: ret i1 [[OR1]]
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;
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%1 = and i32 %x, 12
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%2 = icmp eq i32 %1, 0
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%3 = and i32 %x, 3
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%4 = icmp ne i32 %3, 1
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%5 = or i1 %2, %4
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ret i1 %5
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}
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; ((X & 12) == 0 | (X & 7) != 1) -> !((X & 12) != 0 & (X & 7) == 1) ->
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; !((X & 15) == 9) -> (X & 15) != 9
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define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_1(i32 %x) {
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; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_1(
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; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 15
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; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i32 [[AND1]], 9
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; CHECK-NEXT: ret i1 [[CMP1]]
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;
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%1 = and i32 %x, 12
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%2 = icmp eq i32 %1, 0
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%3 = and i32 %x, 7
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%4 = icmp ne i32 %3, 1
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%5 = or i1 %2, %4
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ret i1 %5
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}
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; ((X & 14) == 0 | (X & 3) != 1) -> !((X & 14) != 0 & (X & 3) == 1) ->
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; no change.
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define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_1b(i32 %x) {
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|
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_1b(
|
|
; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 14
|
|
; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[AND1]], 0
|
|
; CHECK-NEXT: [[AND2:%.*]] = and i32 %x, 3
|
|
; CHECK-NEXT: [[CMP2:%.*]] = icmp ne i32 [[AND2]], 1
|
|
; CHECK-NEXT: [[OR1:%.*]] = or i1 [[CMP1]], [[CMP2]]
|
|
; CHECK-NEXT: ret i1 [[OR1]]
|
|
;
|
|
%1 = and i32 %x, 14
|
|
%2 = icmp eq i32 %1, 0
|
|
%3 = and i32 %x, 3
|
|
%4 = icmp ne i32 %3, 1
|
|
%5 = or i1 %2, %4
|
|
ret i1 %5
|
|
}
|
|
|
|
; ((X & 3) == 0 | (X & 7) != 0) -> !((X & 3) != 0 & (X & 7) == 0) ->
|
|
; !(false) -> true
|
|
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_2(i32 %x) {
|
|
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_2(
|
|
; CHECK-NEXT: ret i1 true
|
|
;
|
|
%1 = and i32 %x, 3
|
|
%2 = icmp eq i32 %1, 0
|
|
%3 = and i32 %x, 7
|
|
%4 = icmp ne i32 %3, 0
|
|
%5 = or i1 %2, %4
|
|
ret i1 %5
|
|
}
|
|
|
|
; ((X & 15) == 0 | (X & 7) != 0) -> !((X & 15) != 0 & (X & 7) == 0) ->
|
|
; !((X & 15) == 8) -> (X & 15) != 8
|
|
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_3(i32 %x) {
|
|
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_3(
|
|
; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 15
|
|
; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i32 [[AND1]], 8
|
|
; CHECK-NEXT: ret i1 [[CMP1]]
|
|
;
|
|
%1 = and i32 %x, 15
|
|
%2 = icmp eq i32 %1, 0
|
|
%3 = and i32 %x, 7
|
|
%4 = icmp ne i32 %3, 0
|
|
%5 = or i1 %2, %4
|
|
ret i1 %5
|
|
}
|
|
|
|
; ((X & 15) == 0 | (X & 3) != 0) -> !((X & 15) != 0 & (X & 3) == 0) ->
|
|
; no change.
|
|
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_3b(i32 %x) {
|
|
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_3b(
|
|
; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 15
|
|
; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[AND1]], 0
|
|
; CHECK-NEXT: [[AND2:%.*]] = and i32 %x, 3
|
|
; CHECK-NEXT: [[CMP2:%.*]] = icmp ne i32 [[AND2]], 0
|
|
; CHECK-NEXT: [[OR1:%.*]] = or i1 [[CMP1]], [[CMP2]]
|
|
; CHECK-NEXT: ret i1 [[OR1]]
|
|
;
|
|
%1 = and i32 %x, 15
|
|
%2 = icmp eq i32 %1, 0
|
|
%3 = and i32 %x, 3
|
|
%4 = icmp ne i32 %3, 0
|
|
%5 = or i1 %2, %4
|
|
ret i1 %5
|
|
}
|
|
|
|
; ((X & 255) == 0 | (X & 15) != 8) -> !(((X & 255) != 0 & (X & 15) == 8)) ->
|
|
; !((X & 15) == 8) -> ((X & 15) != 8)
|
|
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_4(i32 %x) {
|
|
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_4(
|
|
; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 15
|
|
; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i32 [[AND1]], 8
|
|
; CHECK-NEXT: ret i1 [[CMP1]]
|
|
;
|
|
%1 = and i32 %x, 255
|
|
%2 = icmp eq i32 %1, 0
|
|
%3 = and i32 %x, 15
|
|
%4 = icmp ne i32 %3, 8
|
|
%5 = or i1 %2, %4
|
|
ret i1 %5
|
|
}
|
|
|
|
; ((X & 15) == 0 | (X & 15) != 8) -> !(((X & 15) != 0 & (X & 15) == 8)) ->
|
|
; !((X & 15) == 8) -> ((X & 15) != 8)
|
|
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_5(i32 %x) {
|
|
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_5(
|
|
; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 15
|
|
; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i32 [[AND1]], 8
|
|
; CHECK-NEXT: ret i1 [[CMP1]]
|
|
;
|
|
%1 = and i32 %x, 15
|
|
%2 = icmp eq i32 %1, 0
|
|
%3 = and i32 %x, 15
|
|
%4 = icmp ne i32 %3, 8
|
|
%5 = or i1 %2, %4
|
|
ret i1 %5
|
|
}
|
|
|
|
; ((X & 12) == 0 | (X & 15) != 8) -> !(((X & 12) != 0 & (X & 15) == 8)) ->
|
|
; !((X & 15) == 8) -> ((X & 15) != 8
|
|
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_6(i32 %x) {
|
|
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_6(
|
|
; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 15
|
|
; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i32 [[AND1]], 8
|
|
; CHECK-NEXT: ret i1 [[CMP1]]
|
|
;
|
|
%1 = and i32 %x, 12
|
|
%2 = icmp eq i32 %1, 0
|
|
%3 = and i32 %x, 15
|
|
%4 = icmp ne i32 %3, 8
|
|
%5 = or i1 %2, %4
|
|
ret i1 %5
|
|
}
|
|
|
|
; ((X & 7) == 0 | (X & 15) != 8) -> !(((X & 7) != 0 & (X & 15) == 8)) ->
|
|
; !(false) -> true
|
|
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_7(i32 %x) {
|
|
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_7(
|
|
; CHECK-NEXT: ret i1 true
|
|
;
|
|
%1 = and i32 %x, 7
|
|
%2 = icmp eq i32 %1, 0
|
|
%3 = and i32 %x, 15
|
|
%4 = icmp ne i32 %3, 8
|
|
%5 = or i1 %2, %4
|
|
ret i1 %5
|
|
}
|
|
|
|
; ((X & 6) == 0 | (X & 15) != 8) -> !(((X & 6) != 0 & (X & 15) == 8)) ->
|
|
; !(false) -> true
|
|
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_7b(i32 %x) {
|
|
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_7b(
|
|
; CHECK-NEXT: ret i1 true
|
|
;
|
|
%1 = and i32 %x, 6
|
|
%2 = icmp eq i32 %1, 0
|
|
%3 = and i32 %x, 15
|
|
%4 = icmp ne i32 %3, 8
|
|
%5 = or i1 %2, %4
|
|
ret i1 %5
|
|
}
|
|
|
|
|
|
; ((X & 12) != 0 & (X & 3) == 1) -> no change
|
|
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_swapped_0(i32 %x) {
|
|
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_swapped_0(
|
|
; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 12
|
|
; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i32 [[AND1]], 0
|
|
; CHECK-NEXT: [[AND2:%.*]] = and i32 %x, 3
|
|
; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i32 [[AND2]], 1
|
|
; CHECK-NEXT: [[AND3:%.*]] = and i1 [[CMP2]], [[CMP1]]
|
|
; CHECK-NEXT: ret i1 [[AND3]]
|
|
;
|
|
%1 = and i32 %x, 12
|
|
%2 = icmp ne i32 %1, 0
|
|
%3 = and i32 %x, 3
|
|
%4 = icmp eq i32 %3, 1
|
|
%5 = and i1 %4, %2
|
|
ret i1 %5
|
|
}
|
|
|
|
; ((X & 12) != 0 & (X & 7) == 1) -> (X & 15) == 9
|
|
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_swapped_1(i32 %x) {
|
|
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_swapped_1(
|
|
; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 15
|
|
; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[AND1]], 9
|
|
; CHECK-NEXT: ret i1 [[CMP1]]
|
|
;
|
|
%1 = and i32 %x, 12
|
|
%2 = icmp ne i32 %1, 0
|
|
%3 = and i32 %x, 7
|
|
%4 = icmp eq i32 %3, 1
|
|
%5 = and i1 %4, %2
|
|
ret i1 %5
|
|
}
|
|
|
|
; ((X & 14) != 0 & (X & 3) == 1) -> no change
|
|
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_swapped_1b(i32 %x) {
|
|
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_swapped_1b(
|
|
; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 14
|
|
; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i32 [[AND1]], 0
|
|
; CHECK-NEXT: [[AND2:%.*]] = and i32 %x, 3
|
|
; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i32 [[AND2]], 1
|
|
; CHECK-NEXT: [[AND3:%.*]] = and i1 [[CMP2]], [[CMP1]]
|
|
; CHECK-NEXT: ret i1 [[AND3]]
|
|
;
|
|
%1 = and i32 %x, 14
|
|
%2 = icmp ne i32 %1, 0
|
|
%3 = and i32 %x, 3
|
|
%4 = icmp eq i32 %3, 1
|
|
%5 = and i1 %4, %2
|
|
ret i1 %5
|
|
}
|
|
|
|
; ((X & 3) != 0 & (X & 7) == 0) -> false
|
|
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_swapped_2(i32 %x) {
|
|
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_swapped_2(
|
|
; CHECK-NEXT: ret i1 false
|
|
;
|
|
%1 = and i32 %x, 3
|
|
%2 = icmp ne i32 %1, 0
|
|
%3 = and i32 %x, 7
|
|
%4 = icmp eq i32 %3, 0
|
|
%5 = and i1 %4, %2
|
|
ret i1 %5
|
|
}
|
|
|
|
; ((X & 15) != 0 & (X & 7) == 0) -> (X & 15) == 8
|
|
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_swapped_3(i32 %x) {
|
|
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_swapped_3(
|
|
; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 15
|
|
; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[AND1]], 8
|
|
; CHECK-NEXT: ret i1 [[CMP1]]
|
|
;
|
|
%1 = and i32 %x, 15
|
|
%2 = icmp ne i32 %1, 0
|
|
%3 = and i32 %x, 7
|
|
%4 = icmp eq i32 %3, 0
|
|
%5 = and i1 %4, %2
|
|
ret i1 %5
|
|
}
|
|
|
|
; ((X & 15) != 0 & (X & 3) == 0) -> no change
|
|
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_swapped_3b(i32 %x) {
|
|
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_swapped_3b(
|
|
; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 15
|
|
; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i32 [[AND1]], 0
|
|
; CHECK-NEXT: [[AND2:%.*]] = and i32 %x, 3
|
|
; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i32 [[AND2]], 0
|
|
; CHECK-NEXT: [[AND3:%.*]] = and i1 [[CMP2]], [[CMP1]]
|
|
; CHECK-NEXT: ret i1 [[AND3]]
|
|
;
|
|
%1 = and i32 %x, 15
|
|
%2 = icmp ne i32 %1, 0
|
|
%3 = and i32 %x, 3
|
|
%4 = icmp eq i32 %3, 0
|
|
%5 = and i1 %4, %2
|
|
ret i1 %5
|
|
}
|
|
|
|
; ((X & 255) != 0 & (X & 15) == 8) -> (X & 15) == 8
|
|
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_swapped_4(i32 %x) {
|
|
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_swapped_4(
|
|
; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 15
|
|
; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[AND1]], 8
|
|
; CHECK-NEXT: ret i1 [[CMP1]]
|
|
;
|
|
%1 = and i32 %x, 255
|
|
%2 = icmp ne i32 %1, 0
|
|
%3 = and i32 %x, 15
|
|
%4 = icmp eq i32 %3, 8
|
|
%5 = and i1 %4, %2
|
|
ret i1 %5
|
|
}
|
|
|
|
; ((X & 15) != 0 & (X & 15) == 8) -> (X & 15) == 8
|
|
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_swapped_5(i32 %x) {
|
|
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_swapped_5(
|
|
; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 15
|
|
; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[AND1]], 8
|
|
; CHECK-NEXT: ret i1 [[CMP1]]
|
|
;
|
|
%1 = and i32 %x, 15
|
|
%2 = icmp ne i32 %1, 0
|
|
%3 = and i32 %x, 15
|
|
%4 = icmp eq i32 %3, 8
|
|
%5 = and i1 %4, %2
|
|
ret i1 %5
|
|
}
|
|
|
|
; ((X & 12) != 0 & (X & 15) == 8) -> (X & 15) == 8
|
|
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_swapped_6(i32 %x) {
|
|
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_swapped_6(
|
|
; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 15
|
|
; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[AND1]], 8
|
|
; CHECK-NEXT: ret i1 [[CMP1]]
|
|
;
|
|
%1 = and i32 %x, 12
|
|
%2 = icmp ne i32 %1, 0
|
|
%3 = and i32 %x, 15
|
|
%4 = icmp eq i32 %3, 8
|
|
%5 = and i1 %4, %2
|
|
ret i1 %5
|
|
}
|
|
|
|
; ((X & 7) != 0 & (X & 15) == 8) -> false
|
|
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_swapped_7(i32 %x) {
|
|
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_swapped_7(
|
|
; CHECK-NEXT: ret i1 false
|
|
;
|
|
%1 = and i32 %x, 7
|
|
%2 = icmp ne i32 %1, 0
|
|
%3 = and i32 %x, 15
|
|
%4 = icmp eq i32 %3, 8
|
|
%5 = and i1 %4, %2
|
|
ret i1 %5
|
|
}
|
|
|
|
; ((X & 6) != 0 & (X & 15) == 8) -> false
|
|
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_swapped_7b(i32 %x) {
|
|
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_swapped_7b(
|
|
; CHECK-NEXT: ret i1 false
|
|
;
|
|
%1 = and i32 %x, 6
|
|
%2 = icmp ne i32 %1, 0
|
|
%3 = and i32 %x, 15
|
|
%4 = icmp eq i32 %3, 8
|
|
%5 = and i1 %4, %2
|
|
ret i1 %5
|
|
}
|
|
|
|
; ((X & 12) == 0 | (X & 3) != 1) -> !((X & 12) != 0 & (X & 3) == 1)) ->
|
|
; no change
|
|
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_0(i32 %x) {
|
|
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_0(
|
|
; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 12
|
|
; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[AND1]], 0
|
|
; CHECK-NEXT: [[AND2:%.*]] = and i32 %x, 3
|
|
; CHECK-NEXT: [[CMP2:%.*]] = icmp ne i32 [[AND2]], 1
|
|
; CHECK-NEXT: [[OR1:%.*]] = or i1 [[CMP2]], [[CMP1]]
|
|
; CHECK-NEXT: ret i1 [[OR1]]
|
|
;
|
|
%1 = and i32 %x, 12
|
|
%2 = icmp eq i32 %1, 0
|
|
%3 = and i32 %x, 3
|
|
%4 = icmp ne i32 %3, 1
|
|
%5 = or i1 %4, %2
|
|
ret i1 %5
|
|
}
|
|
|
|
; ((X & 12) == 0 | (X & 7) != 1) -> !((X & 12) != 0 & (X & 7) == 1) ->
|
|
; !((X & 15) == 9) -> (X & 15) != 9
|
|
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_1(i32 %x) {
|
|
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_1(
|
|
; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 15
|
|
; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i32 [[AND1]], 9
|
|
; CHECK-NEXT: ret i1 [[CMP1]]
|
|
;
|
|
%1 = and i32 %x, 12
|
|
%2 = icmp eq i32 %1, 0
|
|
%3 = and i32 %x, 7
|
|
%4 = icmp ne i32 %3, 1
|
|
%5 = or i1 %4, %2
|
|
ret i1 %5
|
|
}
|
|
|
|
; ((X & 14) == 0 | (X & 3) != 1) -> !((X & 14) != 0 & (X & 3) == 1) ->
|
|
; no change.
|
|
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_1b(i32 %x) {
|
|
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_1b(
|
|
; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 14
|
|
; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[AND1]], 0
|
|
; CHECK-NEXT: [[AND2:%.*]] = and i32 %x, 3
|
|
; CHECK-NEXT: [[CMP2:%.*]] = icmp ne i32 [[AND2]], 1
|
|
; CHECK-NEXT: [[OR1:%.*]] = or i1 [[CMP2]], [[CMP1]]
|
|
; CHECK-NEXT: ret i1 [[OR1]]
|
|
;
|
|
%1 = and i32 %x, 14
|
|
%2 = icmp eq i32 %1, 0
|
|
%3 = and i32 %x, 3
|
|
%4 = icmp ne i32 %3, 1
|
|
%5 = or i1 %4, %2
|
|
ret i1 %5
|
|
}
|
|
|
|
; ((X & 3) == 0 | (X & 7) != 0) -> !((X & 3) != 0 & (X & 7) == 0) ->
|
|
; !(false) -> true
|
|
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_2(i32 %x) {
|
|
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_2(
|
|
; CHECK-NEXT: ret i1 true
|
|
;
|
|
%1 = and i32 %x, 3
|
|
%2 = icmp eq i32 %1, 0
|
|
%3 = and i32 %x, 7
|
|
%4 = icmp ne i32 %3, 0
|
|
%5 = or i1 %4, %2
|
|
ret i1 %5
|
|
}
|
|
|
|
; ((X & 15) == 0 | (X & 7) != 0) -> !((X & 15) != 0 & (X & 7) == 0) ->
|
|
; !((X & 15) == 8) -> (X & 15) != 8
|
|
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_3(i32 %x) {
|
|
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_3(
|
|
; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 15
|
|
; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i32 [[AND1]], 8
|
|
; CHECK-NEXT: ret i1 [[CMP1]]
|
|
;
|
|
%1 = and i32 %x, 15
|
|
%2 = icmp eq i32 %1, 0
|
|
%3 = and i32 %x, 7
|
|
%4 = icmp ne i32 %3, 0
|
|
%5 = or i1 %4, %2
|
|
ret i1 %5
|
|
}
|
|
|
|
; ((X & 15) == 0 | (X & 3) != 0) -> !((X & 15) != 0 & (X & 3) == 0) ->
|
|
; no change.
|
|
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_3b(i32 %x) {
|
|
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_3b(
|
|
; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 15
|
|
; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[AND1]], 0
|
|
; CHECK-NEXT: [[AND2:%.*]] = and i32 %x, 3
|
|
; CHECK-NEXT: [[CMP2:%.*]] = icmp ne i32 [[AND2]], 0
|
|
; CHECK-NEXT: [[OR1:%.*]] = or i1 [[CMP2]], [[CMP1]]
|
|
; CHECK-NEXT: ret i1 [[OR1]]
|
|
;
|
|
%1 = and i32 %x, 15
|
|
%2 = icmp eq i32 %1, 0
|
|
%3 = and i32 %x, 3
|
|
%4 = icmp ne i32 %3, 0
|
|
%5 = or i1 %4, %2
|
|
ret i1 %5
|
|
}
|
|
|
|
; ((X & 255) == 0 | (X & 15) != 8) -> !(((X & 255) != 0 & (X & 15) == 8)) ->
|
|
; !((X & 15) == 8) -> ((X & 15) != 8)
|
|
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_4(i32 %x) {
|
|
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_4(
|
|
; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 15
|
|
; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i32 [[AND1]], 8
|
|
; CHECK-NEXT: ret i1 [[CMP1]]
|
|
;
|
|
%1 = and i32 %x, 255
|
|
%2 = icmp eq i32 %1, 0
|
|
%3 = and i32 %x, 15
|
|
%4 = icmp ne i32 %3, 8
|
|
%5 = or i1 %4, %2
|
|
ret i1 %5
|
|
}
|
|
|
|
; ((X & 15) == 0 | (X & 15) != 8) -> !(((X & 15) != 0 & (X & 15) == 8)) ->
|
|
; !((X & 15) == 8) -> ((X & 15) != 8)
|
|
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_5(i32 %x) {
|
|
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_5(
|
|
; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 15
|
|
; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i32 [[AND1]], 8
|
|
; CHECK-NEXT: ret i1 [[CMP1]]
|
|
;
|
|
%1 = and i32 %x, 15
|
|
%2 = icmp eq i32 %1, 0
|
|
%3 = and i32 %x, 15
|
|
%4 = icmp ne i32 %3, 8
|
|
%5 = or i1 %4, %2
|
|
ret i1 %5
|
|
}
|
|
|
|
; ((X & 12) == 0 | (X & 15) != 8) -> !(((X & 12) != 0 & (X & 15) == 8)) ->
|
|
; !((X & 15) == 8) -> ((X & 15) != 8
|
|
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_6(i32 %x) {
|
|
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_6(
|
|
; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 15
|
|
; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i32 [[AND1]], 8
|
|
; CHECK-NEXT: ret i1 [[CMP1]]
|
|
;
|
|
%1 = and i32 %x, 12
|
|
%2 = icmp eq i32 %1, 0
|
|
%3 = and i32 %x, 15
|
|
%4 = icmp ne i32 %3, 8
|
|
%5 = or i1 %4, %2
|
|
ret i1 %5
|
|
}
|
|
|
|
; ((X & 7) == 0 | (X & 15) != 8) -> !(((X & 7) != 0 & (X & 15) == 8)) ->
|
|
; !(false) -> true
|
|
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_7(i32 %x) {
|
|
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_7(
|
|
; CHECK-NEXT: ret i1 true
|
|
;
|
|
%1 = and i32 %x, 7
|
|
%2 = icmp eq i32 %1, 0
|
|
%3 = and i32 %x, 15
|
|
%4 = icmp ne i32 %3, 8
|
|
%5 = or i1 %4, %2
|
|
ret i1 %5
|
|
}
|
|
|
|
; ((X & 6) == 0 | (X & 15) != 8) -> !(((X & 6) != 0 & (X & 15) == 8)) ->
|
|
; !(false) -> true
|
|
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_7b(i32 %x) {
|
|
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_7b(
|
|
; CHECK-NEXT: ret i1 true
|
|
;
|
|
%1 = and i32 %x, 6
|
|
%2 = icmp eq i32 %1, 0
|
|
%3 = and i32 %x, 15
|
|
%4 = icmp ne i32 %3, 8
|
|
%5 = or i1 %4, %2
|
|
ret i1 %5
|
|
}
|