Sasa Stankovic 86ebfe24e5 [mips] Don't use odd-numbered float registers for double arguments for fastcc ... calling convention if FP is 64-bit and +nooddspreg is used. Differential Revision: http://reviews.llvm.org/D4981.diff llvm-svn: 216262		2014-08-22 09:23:22 +00:00
..
AArch64	[FastISel][AArch64] Add support for variable shift.	2014-08-21 23:06:07 +00:00
ARM	Add a thread-model knob for lowering atomics on baremetal & single threaded systems	2014-08-21 14:35:47 +00:00
CPP	IR: add "cmpxchg weak" variant to support permitted failure.	2014-06-13 14:24:07 +00:00
Generic	Use "weak alias" instead of "alias weak"	2014-07-30 22:51:54 +00:00
Hexagon	DebugInfo: Assert that any CU for which debug_loc lists are emitted, has at least one range.	2014-08-06 00:21:25 +00:00
Inputs	Debug Info: update testing cases to specify the debug info version number.	2013-11-22 21:49:45 +00:00
MSP430	Reduce verbiage of lit.local.cfg files	2014-06-09 22:42:55 +00:00
Mips	[mips] Don't use odd-numbered float registers for double arguments for fastcc	2014-08-22 09:23:22 +00:00
NVPTX	[NVPTX] Add some extra tests for mul.wide to test non-power-of-two source types	2014-07-23 20:23:49 +00:00
PowerPC	Reapply [FastISel] Let the target decide first if it wants to materialize a constant (215588).	2014-08-19 19:05:24 +00:00
R600	R600/SI: Teach moveToVALU how to handle more S_LOAD_* instructions	2014-08-21 20:41:00 +00:00
SPARC	IR: add "cmpxchg weak" variant to support permitted failure.	2014-06-13 14:24:07 +00:00
SystemZ	IR: add "cmpxchg weak" variant to support permitted failure.	2014-06-13 14:24:07 +00:00
Thumb	Thumb1 load/store optimizer: Improve code to materialize new base register.	2014-08-21 17:11:03 +00:00
Thumb2	[ARM] Enable DP copy, load and store instructions for FPv4-SP	2014-08-21 12:50:31 +00:00
X86	DAGCombiner: Make concat_vector combine safe for EVTs and concat_vectors with many arguments.	2014-08-21 13:28:02 +00:00
XCore	llvm/test/CodeGen/XCore/dwarf_debug.ll: Fix not to be affected by *-win32.	2014-07-04 11:58:03 +00:00