forked from OSchip/llvm-project
170 lines
4.7 KiB
LLVM
170 lines
4.7 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,CI %s
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; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SI %s
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; GCN-LABEL: {{^}}mad_i64_i32_sextops:
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; CI: v_mad_i64_i32 v[0:1], s[6:7], v0, v1, v[2:3]
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; SI: v_mul_lo_u32
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; SI: v_mul_hi_i32
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; SI: v_add_i32
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; SI: v_addc_u32
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define i64 @mad_i64_i32_sextops(i32 %arg0, i32 %arg1, i64 %arg2) #0 {
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%sext0 = sext i32 %arg0 to i64
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%sext1 = sext i32 %arg1 to i64
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%mul = mul i64 %sext0, %sext1
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%mad = add i64 %mul, %arg2
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ret i64 %mad
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}
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; GCN-LABEL: {{^}}mad_i64_i32_sextops_commute:
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; CI: v_mad_i64_i32 v[0:1], s[6:7], v0, v1, v[2:3]
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; SI-DAG: v_mul_lo_u32
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; SI-DAG: v_mul_hi_i32
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; SI: v_add_i32
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; SI: v_addc_u32
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define i64 @mad_i64_i32_sextops_commute(i32 %arg0, i32 %arg1, i64 %arg2) #0 {
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%sext0 = sext i32 %arg0 to i64
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%sext1 = sext i32 %arg1 to i64
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%mul = mul i64 %sext0, %sext1
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%mad = add i64 %arg2, %mul
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ret i64 %mad
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}
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; GCN-LABEL: {{^}}mad_u64_u32_zextops:
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; CI: v_mad_u64_u32 v[0:1], s[6:7], v0, v1, v[2:3]
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; SI-DAG: v_mul_lo_u32
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; SI-DAG: v_mul_hi_u32
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; SI: v_add_i32
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; SI: v_addc_u32
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define i64 @mad_u64_u32_zextops(i32 %arg0, i32 %arg1, i64 %arg2) #0 {
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%sext0 = zext i32 %arg0 to i64
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%sext1 = zext i32 %arg1 to i64
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%mul = mul i64 %sext0, %sext1
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%mad = add i64 %mul, %arg2
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ret i64 %mad
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}
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; GCN-LABEL: {{^}}mad_u64_u32_zextops_commute:
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; CI: v_mad_u64_u32 v[0:1], s[6:7], v0, v1, v[2:3]
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; SI-DAG: v_mul_lo_u32
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; SI-DAG: v_mul_hi_u32
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; SI: v_add_i32
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; SI: v_addc_u32
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define i64 @mad_u64_u32_zextops_commute(i32 %arg0, i32 %arg1, i64 %arg2) #0 {
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%sext0 = zext i32 %arg0 to i64
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%sext1 = zext i32 %arg1 to i64
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%mul = mul i64 %sext0, %sext1
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%mad = add i64 %arg2, %mul
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ret i64 %mad
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}
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; GCN-LABEL: {{^}}mad_i64_i32_sextops_i32_i128:
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; CI: v_mad_u64_u32
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; CI: v_mad_u64_u32
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; CI: v_mad_i64_i32
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; CI: v_mad_u64_u32
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; SI-NOT: v_mad_
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define i128 @mad_i64_i32_sextops_i32_i128(i32 %arg0, i32 %arg1, i128 %arg2) #0 {
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%sext0 = sext i32 %arg0 to i128
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%sext1 = sext i32 %arg1 to i128
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%mul = mul i128 %sext0, %sext1
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%mad = add i128 %mul, %arg2
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ret i128 %mad
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}
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; GCN-LABEL: {{^}}mad_i64_i32_sextops_i32_i63:
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; CI: v_lshl_b64
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; CI: v_ashr
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; CI: v_mad_i64_i32 v[0:1], s[6:7], v0, v1, v[2:3]
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; SI-NOT: v_mad_u64_u32
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define i63 @mad_i64_i32_sextops_i32_i63(i32 %arg0, i32 %arg1, i63 %arg2) #0 {
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%sext0 = sext i32 %arg0 to i63
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%sext1 = sext i32 %arg1 to i63
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%mul = mul i63 %sext0, %sext1
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%mad = add i63 %mul, %arg2
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ret i63 %mad
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}
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; GCN-LABEL: {{^}}mad_i64_i32_sextops_i31_i63:
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; CI: v_lshl_b64
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; CI: v_bfe_i32 v[[B1:[0-9]+]], v1, 0, 31
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; CI: v_ashr_i64
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; CI: v_bfe_i32 v[[B2:[0-9]+]], v0, 0, 31
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; CI: v_mad_i64_i32 v[0:1], s[6:7], v[[B2]], v[[B1]], v[1:2]
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define i63 @mad_i64_i32_sextops_i31_i63(i31 %arg0, i31 %arg1, i63 %arg2) #0 {
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%sext0 = sext i31 %arg0 to i63
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%sext1 = sext i31 %arg1 to i63
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%mul = mul i63 %sext0, %sext1
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%mad = add i63 %mul, %arg2
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ret i63 %mad
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}
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; GCN-LABEL: {{^}}mad_u64_u32_bitops:
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; CI: v_mad_u64_u32 v[0:1], s[6:7], v0, v2, v[4:5]
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define i64 @mad_u64_u32_bitops(i64 %arg0, i64 %arg1, i64 %arg2) #0 {
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%trunc.lhs = and i64 %arg0, 4294967295
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%trunc.rhs = and i64 %arg1, 4294967295
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%mul = mul i64 %trunc.lhs, %trunc.rhs
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%add = add i64 %mul, %arg2
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ret i64 %add
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}
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; GCN-LABEL: {{^}}mad_u64_u32_bitops_lhs_mask_small:
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; GCN-NOT: v_mad_
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define i64 @mad_u64_u32_bitops_lhs_mask_small(i64 %arg0, i64 %arg1, i64 %arg2) #0 {
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%trunc.lhs = and i64 %arg0, 8589934591
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%trunc.rhs = and i64 %arg1, 4294967295
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%mul = mul i64 %trunc.lhs, %trunc.rhs
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%add = add i64 %mul, %arg2
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ret i64 %add
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}
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; GCN-LABEL: {{^}}mad_u64_u32_bitops_rhs_mask_small:
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; GCN-NOT: v_mad_
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define i64 @mad_u64_u32_bitops_rhs_mask_small(i64 %arg0, i64 %arg1, i64 %arg2) #0 {
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%trunc.lhs = and i64 %arg0, 4294967295
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%trunc.rhs = and i64 %arg1, 8589934591
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%mul = mul i64 %trunc.lhs, %trunc.rhs
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%add = add i64 %mul, %arg2
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ret i64 %add
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}
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; GCN-LABEL: {{^}}mad_i64_i32_bitops:
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; CI: v_mad_i64_i32 v[0:1], s[6:7], v0, v2, v[4:5]
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; SI-NOT: v_mad_
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define i64 @mad_i64_i32_bitops(i64 %arg0, i64 %arg1, i64 %arg2) #0 {
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%shl.lhs = shl i64 %arg0, 32
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%trunc.lhs = ashr i64 %shl.lhs, 32
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%shl.rhs = shl i64 %arg1, 32
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%trunc.rhs = ashr i64 %shl.rhs, 32
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%mul = mul i64 %trunc.lhs, %trunc.rhs
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%add = add i64 %mul, %arg2
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ret i64 %add
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}
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; Example from bug report
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; GCN-LABEL: {{^}}mad_i64_i32_unpack_i64ops:
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; CI: v_mad_u64_u32 v[0:1], s[6:7], v1, v0, v[0:1]
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; SI-NOT: v_mad_u64_u32
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define i64 @mad_i64_i32_unpack_i64ops(i64 %arg0) #0 {
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%tmp4 = lshr i64 %arg0, 32
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%tmp5 = and i64 %arg0, 4294967295
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%mul = mul nuw i64 %tmp4, %tmp5
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%mad = add i64 %mul, %arg0
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ret i64 %mad
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}
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone speculatable }
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