llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-frame-index.mir

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
--- |
target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5"
define void @test_frame_index_p5() {
%ptr0 = alloca i32, addrspace(5)
ret void
}
...
---
name: test_frame_index_p5
legalized: true
stack:
- { id: 0, name: ptr0, offset: 0, size: 4, alignment: 4 }
body: |
bb.0:
; CHECK-LABEL: name: test_frame_index_p5
; CHECK: [[FRAME_INDEX:%[0-9]+]]:sgpr(p5) = G_FRAME_INDEX %stack.0.ptr0
%0:_(p5) = G_FRAME_INDEX %stack.0.ptr0
...