llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fabs.mir

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
---
name: fabs_s
legalized: true
body: |
bb.0:
liveins: $sgpr0_sgpr1
; CHECK-LABEL: name: fabs_s
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[FABS:%[0-9]+]]:sgpr(s32) = G_FABS [[COPY]]
; CHECK: $vgpr0 = COPY [[FABS]](s32)
%0:_(s32) = COPY $sgpr0
%1:_(s32) = G_FABS %0
$vgpr0 = COPY %1
...
---
name: fabs_v
legalized: true
body: |
bb.0:
liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: fabs_v
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[FABS:%[0-9]+]]:vgpr(s32) = G_FABS [[COPY]]
; CHECK: $vgpr0 = COPY [[FABS]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = G_FABS %0
$vgpr0 = COPY %1
...