forked from OSchip/llvm-project
199 lines
6.9 KiB
YAML
199 lines
6.9 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
|
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck %s
|
|
|
|
---
|
|
name: test_zext_s32_to_s64
|
|
body: |
|
|
bb.0:
|
|
liveins: $vgpr0
|
|
|
|
; CHECK-LABEL: name: test_zext_s32_to_s64
|
|
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
|
|
; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s32)
|
|
; CHECK: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
|
|
%0:_(s32) = COPY $vgpr0
|
|
%1:_(s64) = G_ZEXT %0
|
|
$vgpr0_vgpr1 = COPY %1
|
|
...
|
|
|
|
---
|
|
name: test_zext_s16_to_s64
|
|
body: |
|
|
bb.0:
|
|
liveins: $vgpr0
|
|
|
|
; CHECK-LABEL: name: test_zext_s16_to_s64
|
|
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
|
|
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535
|
|
; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s32)
|
|
; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C]]
|
|
; CHECK: $vgpr0_vgpr1 = COPY [[AND]](s64)
|
|
%0:_(s32) = COPY $vgpr0
|
|
%1:_(s16) = G_TRUNC %0
|
|
%2:_(s64) = G_ZEXT %1
|
|
$vgpr0_vgpr1 = COPY %2
|
|
...
|
|
|
|
---
|
|
name: test_zext_s16_to_s32
|
|
body: |
|
|
bb.0:
|
|
liveins: $vgpr0
|
|
|
|
; CHECK-LABEL: name: test_zext_s16_to_s32
|
|
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
|
|
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
|
|
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
|
|
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
|
|
; CHECK: $vgpr0 = COPY [[AND]](s32)
|
|
%0:_(s32) = COPY $vgpr0
|
|
%1:_(s16) = G_TRUNC %0
|
|
%2:_(s32) = G_ZEXT %1
|
|
$vgpr0 = COPY %2
|
|
...
|
|
|
|
---
|
|
name: test_zext_i1_to_s32
|
|
body: |
|
|
bb.0:
|
|
|
|
; CHECK-LABEL: name: test_zext_i1_to_s32
|
|
; CHECK: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
|
|
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[C]](s1)
|
|
; CHECK: $vgpr0 = COPY [[ZEXT]](s32)
|
|
%0:_(s1) = G_CONSTANT i1 0
|
|
%1:_(s32) = G_ZEXT %0
|
|
$vgpr0 = COPY %1
|
|
...
|
|
|
|
---
|
|
name: test_zext_i1_to_i64
|
|
body: |
|
|
bb.0:
|
|
|
|
; CHECK-LABEL: name: test_zext_i1_to_i64
|
|
; CHECK: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
|
|
; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[C]](s1)
|
|
; CHECK: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
|
|
%0:_(s1) = G_CONSTANT i1 0
|
|
%1:_(s64) = G_ZEXT %0
|
|
$vgpr0_vgpr1 = COPY %1
|
|
...
|
|
|
|
---
|
|
name: test_zext_v2s16_to_v2s32
|
|
body: |
|
|
bb.0:
|
|
liveins: $vgpr0
|
|
|
|
; CHECK-LABEL: name: test_zext_v2s16_to_v2s32
|
|
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
|
|
; CHECK: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<2 x s16>)
|
|
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[UV]](s16)
|
|
; CHECK: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[UV1]](s16)
|
|
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ZEXT]](s32), [[ZEXT1]](s32)
|
|
; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
|
|
%0:_(<2 x s16>) = COPY $vgpr0
|
|
%1:_(<2 x s32>) = G_ZEXT %0
|
|
$vgpr0_vgpr1 = COPY %1
|
|
...
|
|
|
|
---
|
|
name: test_zext_v3s16_to_v3s32
|
|
body: |
|
|
bb.0:
|
|
liveins: $vgpr0_vgpr1
|
|
|
|
; CHECK-LABEL: name: test_zext_v3s16_to_v3s32
|
|
; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
|
|
; CHECK: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[COPY]](<4 x s16>), 0
|
|
; CHECK: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[EXTRACT]](<3 x s16>)
|
|
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[UV]](s16)
|
|
; CHECK: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[UV1]](s16)
|
|
; CHECK: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[UV2]](s16)
|
|
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[ZEXT]](s32), [[ZEXT1]](s32), [[ZEXT2]](s32)
|
|
; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
|
|
%0:_(<4 x s16>) = COPY $vgpr0_vgpr1
|
|
%1:_(<3 x s16>) = G_EXTRACT %0, 0
|
|
%2:_(<3 x s32>) = G_ZEXT %1
|
|
$vgpr0_vgpr1_vgpr2 = COPY %2
|
|
...
|
|
|
|
---
|
|
name: test_zext_v4s16_to_v4s32
|
|
body: |
|
|
bb.0:
|
|
liveins: $vgpr0_vgpr1
|
|
|
|
; CHECK-LABEL: name: test_zext_v4s16_to_v4s32
|
|
; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
|
|
; CHECK: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
|
|
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[UV]](s16)
|
|
; CHECK: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[UV1]](s16)
|
|
; CHECK: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[UV2]](s16)
|
|
; CHECK: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[UV3]](s16)
|
|
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[ZEXT]](s32), [[ZEXT1]](s32), [[ZEXT2]](s32), [[ZEXT3]](s32)
|
|
; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
|
|
%0:_(<4 x s16>) = COPY $vgpr0_vgpr1
|
|
%1:_(<4 x s32>) = G_ZEXT %0
|
|
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %1
|
|
...
|
|
|
|
---
|
|
name: test_zext_v2s32_to_v2s64
|
|
body: |
|
|
bb.0:
|
|
liveins: $vgpr0_vgpr1
|
|
|
|
; CHECK-LABEL: name: test_zext_v2s32_to_v2s64
|
|
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
|
|
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
|
|
; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[UV]](s32)
|
|
; CHECK: [[ZEXT1:%[0-9]+]]:_(s64) = G_ZEXT [[UV1]](s32)
|
|
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[ZEXT]](s64), [[ZEXT1]](s64)
|
|
; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
|
|
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
|
|
%1:_(<2 x s64>) = G_ZEXT %0
|
|
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %1
|
|
...
|
|
|
|
---
|
|
name: test_zext_v3s32_to_v3s64
|
|
body: |
|
|
bb.0:
|
|
liveins: $vgpr0_vgpr1_vgpr2
|
|
|
|
; CHECK-LABEL: name: test_zext_v3s32_to_v3s64
|
|
; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
|
|
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
|
|
; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[UV]](s32)
|
|
; CHECK: [[ZEXT1:%[0-9]+]]:_(s64) = G_ZEXT [[UV1]](s32)
|
|
; CHECK: [[ZEXT2:%[0-9]+]]:_(s64) = G_ZEXT [[UV2]](s32)
|
|
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s64>) = G_BUILD_VECTOR [[ZEXT]](s64), [[ZEXT1]](s64), [[ZEXT2]](s64)
|
|
; CHECK: S_NOP 0, implicit [[BUILD_VECTOR]](<3 x s64>)
|
|
%0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
|
|
%1:_(<3 x s64>) = G_ZEXT %0
|
|
S_NOP 0, implicit %1
|
|
|
|
...
|
|
|
|
---
|
|
name: test_zext_v4s32_to_v4s64
|
|
body: |
|
|
bb.0:
|
|
liveins: $vgpr0_vgpr1_vgpr2_vgpr3
|
|
|
|
; CHECK-LABEL: name: test_zext_v4s32_to_v4s64
|
|
; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
|
|
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)
|
|
; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[UV]](s32)
|
|
; CHECK: [[ZEXT1:%[0-9]+]]:_(s64) = G_ZEXT [[UV1]](s32)
|
|
; CHECK: [[ZEXT2:%[0-9]+]]:_(s64) = G_ZEXT [[UV2]](s32)
|
|
; CHECK: [[ZEXT3:%[0-9]+]]:_(s64) = G_ZEXT [[UV3]](s32)
|
|
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[ZEXT]](s64), [[ZEXT1]](s64), [[ZEXT2]](s64), [[ZEXT3]](s64)
|
|
; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<4 x s64>)
|
|
%0:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
|
|
%1:_(<4 x s64>) = G_ZEXT %0
|
|
$vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY %1
|
|
...
|