maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/llvm/test/MC
History
Yonghong Song ce96738dee bpf: print backward branch target properly 
Currently, it prints the backward branch offset as unsigned value
like below:
       7:       7d 34 0b 00 00 00 00 00         if r4 s>= r3 goto 11 <LBB0_3>
       8:       b7 00 00 00 00 00 00 00         r0 = 0
LBB0_2:
       9:       07 00 00 00 01 00 00 00         r0 += 1
      ......
      17:       bf 31 00 00 00 00 00 00         r1 = r3
      18:       6d 32 f6 ff 00 00 00 00         if r2 s> r3 goto 65526 <LBB0_3+0x7FFB0>

The correct print insn 18 should be:
      18:       6d 32 f6 ff 00 00 00 00         if r2 s> r3 goto -10 <LBB0_2>

To provide better clarity and be consistent with kernel verifier output,
the insn 7 output is changed to the following with "+" added to
non-negative branch offset:
       7:       7d 34 0b 00 00 00 00 00         if r4 s>= r3 goto +11 <LBB0_3>

Signed-off-by: Yonghong Song <yhs@fb.com>
Acked-by: Alexei Starovoitov <ast@kernel.org>
llvm-svn: 318442
 		2017-11-16 19:15:36 +00:00
..
AArch64 [AArch64][SVE] Asm: Report SVE parsing diagnostics only once 2017-11-15 15:44:43 +00:00
AMDGPU AMDGPU: Rename MaxFlatWorkgroupSize to MaxFlatWorkGroupSize for consistency 2017-10-18 17:31:09 +00:00
ARM [ARM] Tighten up CHECK lines in a test 2017-10-24 14:20:13 +00:00
AVR [AVR] Remove a bunch of now-obselete tests 2017-07-01 05:23:13 +00:00
AsmParser Give a test a triple 2017-10-10 01:34:31 +00:00
BPF bpf: print backward branch target properly 2017-11-16 19:15:36 +00:00
COFF [codeview] Implement FPO data assembler directives 2017-10-11 21:24:33 +00:00
Disassembler Reland "[mips][mt][6/7] Add support for mftr, mttr instructions." 2017-11-14 22:26:42 +00:00
ELF llvm-dwarfdump: Make -brief the default and add a -verbose option instead. 2017-09-11 23:05:20 +00:00
Hexagon [Hexagon] New HVX target features. 2017-10-18 18:07:07 +00:00
Lanai [lanai] Add more tests for assembly of conditional ALU ops 2016-07-11 17:58:16 +00:00
MachO [dwarfdump] Add verbose output for .debug-line section 2017-09-21 20:15:30 +00:00
Markup
…
Mips [mips][mt] Add missing test cases from r318207 2017-11-16 10:50:44 +00:00
PowerPC PowerPC: support the separator character in the IAS 2017-10-24 16:19:56 +00:00
RISCV [RISCV] MC layer support for the standard RV32A instruction set extension 2017-11-09 15:00:03 +00:00
Sparc [Sparc] invalid adjustments in TLS_LE/TLS_LDO relocations removed 2017-07-25 15:28:28 +00:00
SystemZ [SystemZ, AsmParser] Enable the mnemonic spell corrector. 2017-07-18 09:17:00 +00:00
WebAssembly [WebAssembly] MC: Don't allow zero sized data segments 2017-10-27 00:08:55 +00:00
X86 [X86] Limit NOPs to 7 bytes when 'slm' is spelled 'silvermont'. 2017-11-13 08:17:30 +00:00