| .. |
|
AArch64
|
[AArch64][AsmParser] Unify code for parsing Neon/SVE vectors.
|
2018-04-11 07:36:10 +00:00 |
|
AMDGPU
|
[AMDGPU][MC][GFX9] Added v_screen_partition_4se_b32
|
2018-04-11 13:13:30 +00:00 |
|
ARM
|
[ARM] Do not convert some vmov instructions
|
2018-04-04 08:54:19 +00:00 |
|
AVR
|
[AVR] Implement some missing code paths
|
2017-12-11 11:01:27 +00:00 |
|
AsmParser
|
Use .set instead of = when printing assignment in assembly output
|
2018-03-27 16:44:41 +00:00 |
|
BPF
|
bpf: New disassembler testcases for 32-bit subregister support
|
2018-02-23 23:49:35 +00:00 |
|
COFF
|
[IR] Avoid the need to prefix MS C++ symbols with '\01'
|
2018-03-16 20:13:32 +00:00 |
|
Disassembler
|
[mips] Correct the predicates for special nops, tlb ctrl instrs, software breakpoint and prefx.
|
2018-04-12 12:37:02 +00:00 |
|
ELF
|
[DWARFv5] Fuss with asm syntax for conveying MD5 checksum.
|
2018-04-11 15:14:05 +00:00 |
|
Hexagon
|
[Hexagon] Recognize and handle :endloop01
|
2018-03-30 15:29:47 +00:00 |
|
Lanai
|
…
|
|
|
MachO
|
[DebugInfo] Support DWARF v5 source code embedding extension
|
2018-02-23 23:01:06 +00:00 |
|
Mips
|
[mips] Correct the predicates of the load/store (double)word for coprocessor 3.
|
2018-04-12 14:41:38 +00:00 |
|
PowerPC
|
[PowerPC] Code cleanup. Remove instructions that were withdrawn from Power 9.
|
2018-02-23 15:55:16 +00:00 |
|
RISCV
|
[RISCV] Add c.mv rs1, rs2 pattern for addi rs1, rs2, 0
|
2018-04-12 19:22:40 +00:00 |
|
Sparc
|
[Sparc] invalid adjustments in TLS_LE/TLS_LDO relocations removed
|
2017-07-25 15:28:28 +00:00 |
|
SystemZ
|
[SystemZ, AsmParser] Enable the mnemonic spell corrector.
|
2017-07-18 09:17:00 +00:00 |
|
WebAssembly
|
[WebAssembly] libObject: Don't include the name the size of custom sections
|
2018-04-12 20:31:12 +00:00 |
|
X86
|
[X86] Describe wbnoinvd instruction
|
2018-04-11 20:01:57 +00:00 |
9745afa674