forked from OSchip/llvm-project
456 lines
16 KiB
LLVM
456 lines
16 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=x86-64 -mattr=+bmi2 | FileCheck %s --check-prefix=CHECK --check-prefix=GENERIC
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=haswell | FileCheck %s --check-prefix=CHECK --check-prefix=HASWELL
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=skylake | FileCheck %s --check-prefix=CHECK --check-prefix=HASWELL
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=knl | FileCheck %s --check-prefix=CHECK --check-prefix=HASWELL
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=znver1 | FileCheck %s --check-prefix=CHECK --check-prefix=ZNVER1
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define i32 @test_bzhi_i32(i32 %a0, i32 %a1, i32 *%a2) {
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; GENERIC-LABEL: test_bzhi_i32:
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; GENERIC: # BB#0:
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; GENERIC-NEXT: bzhil %edi, (%rdx), %ecx
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; GENERIC-NEXT: bzhil %edi, %esi, %eax
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; GENERIC-NEXT: addl %ecx, %eax # sched: [1:0.33]
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; GENERIC-NEXT: retq # sched: [1:1.00]
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;
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; HASWELL-LABEL: test_bzhi_i32:
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; HASWELL: # BB#0:
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; HASWELL-NEXT: bzhil %edi, (%rdx), %ecx # sched: [4:0.50]
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; HASWELL-NEXT: bzhil %edi, %esi, %eax # sched: [1:0.50]
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; HASWELL-NEXT: addl %ecx, %eax # sched: [1:0.25]
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; HASWELL-NEXT: retq # sched: [1:1.00]
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;
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; ZNVER1-LABEL: test_bzhi_i32:
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; ZNVER1: # BB#0:
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; ZNVER1-NEXT: bzhil %edi, (%rdx), %ecx
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; ZNVER1-NEXT: bzhil %edi, %esi, %eax
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; ZNVER1-NEXT: addl %ecx, %eax # sched: [1:0.25]
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; ZNVER1-NEXT: retq # sched: [5:0.50]
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%1 = load i32, i32 *%a2
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%2 = tail call i32 @llvm.x86.bmi.bzhi.32(i32 %1, i32 %a0)
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%3 = tail call i32 @llvm.x86.bmi.bzhi.32(i32 %a1, i32 %a0)
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%4 = add i32 %2, %3
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ret i32 %4
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}
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declare i32 @llvm.x86.bmi.bzhi.32(i32, i32)
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define i64 @test_bzhi_i64(i64 %a0, i64 %a1, i64 *%a2) {
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; GENERIC-LABEL: test_bzhi_i64:
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; GENERIC: # BB#0:
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; GENERIC-NEXT: bzhiq %rdi, (%rdx), %rcx
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; GENERIC-NEXT: bzhiq %rdi, %rsi, %rax
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; GENERIC-NEXT: addq %rcx, %rax # sched: [1:0.33]
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; GENERIC-NEXT: retq # sched: [1:1.00]
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;
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; HASWELL-LABEL: test_bzhi_i64:
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; HASWELL: # BB#0:
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; HASWELL-NEXT: bzhiq %rdi, (%rdx), %rcx # sched: [4:0.50]
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; HASWELL-NEXT: bzhiq %rdi, %rsi, %rax # sched: [1:0.50]
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; HASWELL-NEXT: addq %rcx, %rax # sched: [1:0.25]
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; HASWELL-NEXT: retq # sched: [1:1.00]
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;
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; ZNVER1-LABEL: test_bzhi_i64:
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; ZNVER1: # BB#0:
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; ZNVER1-NEXT: bzhiq %rdi, (%rdx), %rcx
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; ZNVER1-NEXT: bzhiq %rdi, %rsi, %rax
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; ZNVER1-NEXT: addq %rcx, %rax # sched: [1:0.25]
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; ZNVER1-NEXT: retq # sched: [5:0.50]
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%1 = load i64, i64 *%a2
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%2 = tail call i64 @llvm.x86.bmi.bzhi.64(i64 %1, i64 %a0)
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%3 = tail call i64 @llvm.x86.bmi.bzhi.64(i64 %a1, i64 %a0)
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%4 = add i64 %2, %3
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ret i64 %4
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}
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declare i64 @llvm.x86.bmi.bzhi.64(i64, i64)
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; TODO test_mulx_i32
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define i64 @test_mulx_i64(i64 %a0, i64 %a1, i64 *%a2) {
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; GENERIC-LABEL: test_mulx_i64:
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; GENERIC: # BB#0:
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; GENERIC-NEXT: movq %rdx, %rax # sched: [1:0.33]
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; GENERIC-NEXT: movq %rdi, %rdx # sched: [1:0.33]
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; GENERIC-NEXT: mulxq %rsi, %rsi, %rcx # sched: [3:1.00]
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; GENERIC-NEXT: mulxq (%rax), %rdx, %rax # sched: [7:1.00]
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; GENERIC-NEXT: orq %rcx, %rax # sched: [1:0.33]
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; GENERIC-NEXT: retq # sched: [1:1.00]
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;
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; HASWELL-LABEL: test_mulx_i64:
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; HASWELL: # BB#0:
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; HASWELL-NEXT: movq %rdx, %rax # sched: [1:0.25]
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; HASWELL-NEXT: movq %rdi, %rdx # sched: [1:0.25]
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; HASWELL-NEXT: mulxq %rsi, %rsi, %rcx # sched: [4:1.00]
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; HASWELL-NEXT: mulxq (%rax), %rdx, %rax # sched: [8:1.00]
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; HASWELL-NEXT: orq %rcx, %rax # sched: [1:0.25]
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; HASWELL-NEXT: retq # sched: [1:1.00]
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;
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; ZNVER1-LABEL: test_mulx_i64:
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; ZNVER1: # BB#0:
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; ZNVER1-NEXT: movq %rdx, %rax # sched: [1:0.25]
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; ZNVER1-NEXT: movq %rdi, %rdx # sched: [1:0.25]
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; ZNVER1-NEXT: mulxq %rsi, %rsi, %rcx # sched: [4:2.00]
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; ZNVER1-NEXT: mulxq (%rax), %rdx, %rax # sched: [8:2.00]
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; ZNVER1-NEXT: orq %rcx, %rax # sched: [1:0.25]
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; ZNVER1-NEXT: retq # sched: [5:0.50]
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%1 = load i64, i64 *%a2
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%2 = zext i64 %a0 to i128
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%3 = zext i64 %a1 to i128
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%4 = zext i64 %1 to i128
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%5 = mul i128 %2, %3
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%6 = mul i128 %2, %4
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%7 = lshr i128 %5, 64
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%8 = lshr i128 %6, 64
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%9 = trunc i128 %7 to i64
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%10 = trunc i128 %8 to i64
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%11 = or i64 %9, %10
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ret i64 %11
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}
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define i32 @test_pdep_i32(i32 %a0, i32 %a1, i32 *%a2) {
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; GENERIC-LABEL: test_pdep_i32:
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; GENERIC: # BB#0:
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; GENERIC-NEXT: pdepl (%rdx), %edi, %ecx
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; GENERIC-NEXT: pdepl %esi, %edi, %eax
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; GENERIC-NEXT: addl %ecx, %eax # sched: [1:0.33]
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; GENERIC-NEXT: retq # sched: [1:1.00]
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;
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; HASWELL-LABEL: test_pdep_i32:
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; HASWELL: # BB#0:
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; HASWELL-NEXT: pdepl (%rdx), %edi, %ecx # sched: [7:1.00]
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; HASWELL-NEXT: pdepl %esi, %edi, %eax # sched: [3:1.00]
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; HASWELL-NEXT: addl %ecx, %eax # sched: [1:0.25]
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; HASWELL-NEXT: retq # sched: [1:1.00]
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;
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; ZNVER1-LABEL: test_pdep_i32:
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; ZNVER1: # BB#0:
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; ZNVER1-NEXT: pdepl (%rdx), %edi, %ecx
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; ZNVER1-NEXT: pdepl %esi, %edi, %eax
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; ZNVER1-NEXT: addl %ecx, %eax # sched: [1:0.25]
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; ZNVER1-NEXT: retq # sched: [5:0.50]
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%1 = load i32, i32 *%a2
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%2 = tail call i32 @llvm.x86.bmi.pdep.32(i32 %a0, i32 %1)
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%3 = tail call i32 @llvm.x86.bmi.pdep.32(i32 %a0, i32 %a1)
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%4 = add i32 %2, %3
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ret i32 %4
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}
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declare i32 @llvm.x86.bmi.pdep.32(i32, i32)
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define i64 @test_pdep_i64(i64 %a0, i64 %a1, i64 *%a2) {
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; GENERIC-LABEL: test_pdep_i64:
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; GENERIC: # BB#0:
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; GENERIC-NEXT: pdepq (%rdx), %rdi, %rcx
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; GENERIC-NEXT: pdepq %rsi, %rdi, %rax
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; GENERIC-NEXT: addq %rcx, %rax # sched: [1:0.33]
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; GENERIC-NEXT: retq # sched: [1:1.00]
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;
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; HASWELL-LABEL: test_pdep_i64:
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; HASWELL: # BB#0:
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; HASWELL-NEXT: pdepq (%rdx), %rdi, %rcx # sched: [7:1.00]
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; HASWELL-NEXT: pdepq %rsi, %rdi, %rax # sched: [3:1.00]
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; HASWELL-NEXT: addq %rcx, %rax # sched: [1:0.25]
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; HASWELL-NEXT: retq # sched: [1:1.00]
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;
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; ZNVER1-LABEL: test_pdep_i64:
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; ZNVER1: # BB#0:
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; ZNVER1-NEXT: pdepq (%rdx), %rdi, %rcx
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; ZNVER1-NEXT: pdepq %rsi, %rdi, %rax
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; ZNVER1-NEXT: addq %rcx, %rax # sched: [1:0.25]
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; ZNVER1-NEXT: retq # sched: [5:0.50]
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%1 = load i64, i64 *%a2
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%2 = tail call i64 @llvm.x86.bmi.pdep.64(i64 %a0, i64 %1)
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%3 = tail call i64 @llvm.x86.bmi.pdep.64(i64 %a0, i64 %a1)
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%4 = add i64 %2, %3
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ret i64 %4
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}
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declare i64 @llvm.x86.bmi.pdep.64(i64, i64)
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define i32 @test_pext_i32(i32 %a0, i32 %a1, i32 *%a2) {
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; GENERIC-LABEL: test_pext_i32:
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; GENERIC: # BB#0:
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; GENERIC-NEXT: pextl (%rdx), %edi, %ecx
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; GENERIC-NEXT: pextl %esi, %edi, %eax
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; GENERIC-NEXT: addl %ecx, %eax # sched: [1:0.33]
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; GENERIC-NEXT: retq # sched: [1:1.00]
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;
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; HASWELL-LABEL: test_pext_i32:
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; HASWELL: # BB#0:
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; HASWELL-NEXT: pextl (%rdx), %edi, %ecx # sched: [7:1.00]
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; HASWELL-NEXT: pextl %esi, %edi, %eax # sched: [3:1.00]
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; HASWELL-NEXT: addl %ecx, %eax # sched: [1:0.25]
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; HASWELL-NEXT: retq # sched: [1:1.00]
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;
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; ZNVER1-LABEL: test_pext_i32:
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; ZNVER1: # BB#0:
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; ZNVER1-NEXT: pextl (%rdx), %edi, %ecx
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; ZNVER1-NEXT: pextl %esi, %edi, %eax
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; ZNVER1-NEXT: addl %ecx, %eax # sched: [1:0.25]
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; ZNVER1-NEXT: retq # sched: [5:0.50]
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%1 = load i32, i32 *%a2
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%2 = tail call i32 @llvm.x86.bmi.pext.32(i32 %a0, i32 %1)
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%3 = tail call i32 @llvm.x86.bmi.pext.32(i32 %a0, i32 %a1)
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%4 = add i32 %2, %3
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ret i32 %4
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}
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declare i32 @llvm.x86.bmi.pext.32(i32, i32)
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define i64 @test_pext_i64(i64 %a0, i64 %a1, i64 *%a2) {
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; GENERIC-LABEL: test_pext_i64:
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; GENERIC: # BB#0:
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; GENERIC-NEXT: pextq (%rdx), %rdi, %rcx
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; GENERIC-NEXT: pextq %rsi, %rdi, %rax
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; GENERIC-NEXT: addq %rcx, %rax # sched: [1:0.33]
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; GENERIC-NEXT: retq # sched: [1:1.00]
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;
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; HASWELL-LABEL: test_pext_i64:
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; HASWELL: # BB#0:
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; HASWELL-NEXT: pextq (%rdx), %rdi, %rcx # sched: [7:1.00]
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; HASWELL-NEXT: pextq %rsi, %rdi, %rax # sched: [3:1.00]
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; HASWELL-NEXT: addq %rcx, %rax # sched: [1:0.25]
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; HASWELL-NEXT: retq # sched: [1:1.00]
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;
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; ZNVER1-LABEL: test_pext_i64:
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; ZNVER1: # BB#0:
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; ZNVER1-NEXT: pextq (%rdx), %rdi, %rcx
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; ZNVER1-NEXT: pextq %rsi, %rdi, %rax
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; ZNVER1-NEXT: addq %rcx, %rax # sched: [1:0.25]
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; ZNVER1-NEXT: retq # sched: [5:0.50]
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%1 = load i64, i64 *%a2
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%2 = tail call i64 @llvm.x86.bmi.pext.64(i64 %a0, i64 %1)
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%3 = tail call i64 @llvm.x86.bmi.pext.64(i64 %a0, i64 %a1)
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%4 = add i64 %2, %3
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ret i64 %4
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}
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declare i64 @llvm.x86.bmi.pext.64(i64, i64)
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define i32 @test_rorx_i32(i32 %a0, i32 %a1, i32 *%a2) {
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; GENERIC-LABEL: test_rorx_i32:
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; GENERIC: # BB#0:
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; GENERIC-NEXT: rorxl $5, %edi, %ecx # sched: [1:0.50]
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; GENERIC-NEXT: rorxl $5, (%rdx), %eax # sched: [5:0.50]
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; GENERIC-NEXT: addl %ecx, %eax # sched: [1:0.33]
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; GENERIC-NEXT: retq # sched: [1:1.00]
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;
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; HASWELL-LABEL: test_rorx_i32:
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; HASWELL: # BB#0:
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; HASWELL-NEXT: rorxl $5, %edi, %ecx # sched: [1:0.50]
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; HASWELL-NEXT: rorxl $5, (%rdx), %eax # sched: [5:0.50]
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; HASWELL-NEXT: addl %ecx, %eax # sched: [1:0.25]
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; HASWELL-NEXT: retq # sched: [1:1.00]
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;
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; ZNVER1-LABEL: test_rorx_i32:
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; ZNVER1: # BB#0:
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; ZNVER1-NEXT: rorxl $5, (%rdx), %eax # sched: [5:0.50]
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; ZNVER1-NEXT: rorxl $5, %edi, %ecx # sched: [1:0.25]
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; ZNVER1-NEXT: addl %ecx, %eax # sched: [1:0.25]
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; ZNVER1-NEXT: retq # sched: [5:0.50]
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%1 = load i32, i32 *%a2
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%2 = lshr i32 %a0, 5
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%3 = shl i32 %a0, 27
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%4 = or i32 %2, %3
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%5 = lshr i32 %1, 5
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%6 = shl i32 %1, 27
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%7 = or i32 %5, %6
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%8 = add i32 %4, %7
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ret i32 %8
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}
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define i64 @test_rorx_i64(i64 %a0, i64 %a1, i64 *%a2) {
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; GENERIC-LABEL: test_rorx_i64:
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; GENERIC: # BB#0:
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; GENERIC-NEXT: rorxq $5, %rdi, %rcx # sched: [1:0.50]
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; GENERIC-NEXT: rorxq $5, (%rdx), %rax # sched: [5:0.50]
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; GENERIC-NEXT: addq %rcx, %rax # sched: [1:0.33]
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; GENERIC-NEXT: retq # sched: [1:1.00]
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;
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; HASWELL-LABEL: test_rorx_i64:
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; HASWELL: # BB#0:
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; HASWELL-NEXT: rorxq $5, %rdi, %rcx # sched: [1:0.50]
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; HASWELL-NEXT: rorxq $5, (%rdx), %rax # sched: [5:0.50]
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; HASWELL-NEXT: addq %rcx, %rax # sched: [1:0.25]
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; HASWELL-NEXT: retq # sched: [1:1.00]
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;
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; ZNVER1-LABEL: test_rorx_i64:
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; ZNVER1: # BB#0:
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; ZNVER1-NEXT: rorxq $5, (%rdx), %rax # sched: [5:0.50]
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; ZNVER1-NEXT: rorxq $5, %rdi, %rcx # sched: [1:0.25]
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; ZNVER1-NEXT: addq %rcx, %rax # sched: [1:0.25]
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; ZNVER1-NEXT: retq # sched: [5:0.50]
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%1 = load i64, i64 *%a2
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%2 = lshr i64 %a0, 5
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%3 = shl i64 %a0, 59
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%4 = or i64 %2, %3
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%5 = lshr i64 %1, 5
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%6 = shl i64 %1, 59
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%7 = or i64 %5, %6
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%8 = add i64 %4, %7
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ret i64 %8
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}
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define i32 @test_sarx_i32(i32 %a0, i32 %a1, i32 *%a2) {
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; GENERIC-LABEL: test_sarx_i32:
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; GENERIC: # BB#0:
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; GENERIC-NEXT: sarxl %esi, %edi, %ecx # sched: [1:0.50]
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; GENERIC-NEXT: sarxl %esi, (%rdx), %eax # sched: [5:0.50]
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; GENERIC-NEXT: addl %ecx, %eax # sched: [1:0.33]
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; GENERIC-NEXT: retq # sched: [1:1.00]
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;
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; HASWELL-LABEL: test_sarx_i32:
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; HASWELL: # BB#0:
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; HASWELL-NEXT: sarxl %esi, %edi, %ecx # sched: [1:0.50]
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; HASWELL-NEXT: sarxl %esi, (%rdx), %eax # sched: [5:0.50]
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; HASWELL-NEXT: addl %ecx, %eax # sched: [1:0.25]
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; HASWELL-NEXT: retq # sched: [1:1.00]
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;
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; ZNVER1-LABEL: test_sarx_i32:
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; ZNVER1: # BB#0:
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; ZNVER1-NEXT: sarxl %esi, (%rdx), %eax # sched: [5:0.50]
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; ZNVER1-NEXT: sarxl %esi, %edi, %ecx # sched: [1:0.25]
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; ZNVER1-NEXT: addl %ecx, %eax # sched: [1:0.25]
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; ZNVER1-NEXT: retq # sched: [5:0.50]
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%1 = load i32, i32 *%a2
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%2 = ashr i32 %a0, %a1
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%3 = ashr i32 %1, %a1
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%4 = add i32 %2, %3
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ret i32 %4
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}
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define i64 @test_sarx_i64(i64 %a0, i64 %a1, i64 *%a2) {
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; GENERIC-LABEL: test_sarx_i64:
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; GENERIC: # BB#0:
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; GENERIC-NEXT: sarxq %rsi, %rdi, %rcx # sched: [1:0.50]
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; GENERIC-NEXT: sarxq %rsi, (%rdx), %rax # sched: [5:0.50]
|
|
; GENERIC-NEXT: addq %rcx, %rax # sched: [1:0.33]
|
|
; GENERIC-NEXT: retq # sched: [1:1.00]
|
|
;
|
|
; HASWELL-LABEL: test_sarx_i64:
|
|
; HASWELL: # BB#0:
|
|
; HASWELL-NEXT: sarxq %rsi, %rdi, %rcx # sched: [1:0.50]
|
|
; HASWELL-NEXT: sarxq %rsi, (%rdx), %rax # sched: [5:0.50]
|
|
; HASWELL-NEXT: addq %rcx, %rax # sched: [1:0.25]
|
|
; HASWELL-NEXT: retq # sched: [1:1.00]
|
|
;
|
|
; ZNVER1-LABEL: test_sarx_i64:
|
|
; ZNVER1: # BB#0:
|
|
; ZNVER1-NEXT: sarxq %rsi, (%rdx), %rax # sched: [5:0.50]
|
|
; ZNVER1-NEXT: sarxq %rsi, %rdi, %rcx # sched: [1:0.25]
|
|
; ZNVER1-NEXT: addq %rcx, %rax # sched: [1:0.25]
|
|
; ZNVER1-NEXT: retq # sched: [5:0.50]
|
|
%1 = load i64, i64 *%a2
|
|
%2 = ashr i64 %a0, %a1
|
|
%3 = ashr i64 %1, %a1
|
|
%4 = add i64 %2, %3
|
|
ret i64 %4
|
|
}
|
|
|
|
define i32 @test_shlx_i32(i32 %a0, i32 %a1, i32 *%a2) {
|
|
; GENERIC-LABEL: test_shlx_i32:
|
|
; GENERIC: # BB#0:
|
|
; GENERIC-NEXT: shlxl %esi, %edi, %ecx # sched: [1:0.50]
|
|
; GENERIC-NEXT: shlxl %esi, (%rdx), %eax # sched: [5:0.50]
|
|
; GENERIC-NEXT: addl %ecx, %eax # sched: [1:0.33]
|
|
; GENERIC-NEXT: retq # sched: [1:1.00]
|
|
;
|
|
; HASWELL-LABEL: test_shlx_i32:
|
|
; HASWELL: # BB#0:
|
|
; HASWELL-NEXT: shlxl %esi, %edi, %ecx # sched: [1:0.50]
|
|
; HASWELL-NEXT: shlxl %esi, (%rdx), %eax # sched: [5:0.50]
|
|
; HASWELL-NEXT: addl %ecx, %eax # sched: [1:0.25]
|
|
; HASWELL-NEXT: retq # sched: [1:1.00]
|
|
;
|
|
; ZNVER1-LABEL: test_shlx_i32:
|
|
; ZNVER1: # BB#0:
|
|
; ZNVER1-NEXT: shlxl %esi, (%rdx), %eax # sched: [5:0.50]
|
|
; ZNVER1-NEXT: shlxl %esi, %edi, %ecx # sched: [1:0.25]
|
|
; ZNVER1-NEXT: addl %ecx, %eax # sched: [1:0.25]
|
|
; ZNVER1-NEXT: retq # sched: [5:0.50]
|
|
%1 = load i32, i32 *%a2
|
|
%2 = shl i32 %a0, %a1
|
|
%3 = shl i32 %1, %a1
|
|
%4 = add i32 %2, %3
|
|
ret i32 %4
|
|
}
|
|
|
|
define i64 @test_shlx_i64(i64 %a0, i64 %a1, i64 *%a2) {
|
|
; GENERIC-LABEL: test_shlx_i64:
|
|
; GENERIC: # BB#0:
|
|
; GENERIC-NEXT: shlxq %rsi, %rdi, %rcx # sched: [1:0.50]
|
|
; GENERIC-NEXT: shlxq %rsi, (%rdx), %rax # sched: [5:0.50]
|
|
; GENERIC-NEXT: addq %rcx, %rax # sched: [1:0.33]
|
|
; GENERIC-NEXT: retq # sched: [1:1.00]
|
|
;
|
|
; HASWELL-LABEL: test_shlx_i64:
|
|
; HASWELL: # BB#0:
|
|
; HASWELL-NEXT: shlxq %rsi, %rdi, %rcx # sched: [1:0.50]
|
|
; HASWELL-NEXT: shlxq %rsi, (%rdx), %rax # sched: [5:0.50]
|
|
; HASWELL-NEXT: addq %rcx, %rax # sched: [1:0.25]
|
|
; HASWELL-NEXT: retq # sched: [1:1.00]
|
|
;
|
|
; ZNVER1-LABEL: test_shlx_i64:
|
|
; ZNVER1: # BB#0:
|
|
; ZNVER1-NEXT: shlxq %rsi, (%rdx), %rax # sched: [5:0.50]
|
|
; ZNVER1-NEXT: shlxq %rsi, %rdi, %rcx # sched: [1:0.25]
|
|
; ZNVER1-NEXT: addq %rcx, %rax # sched: [1:0.25]
|
|
; ZNVER1-NEXT: retq # sched: [5:0.50]
|
|
%1 = load i64, i64 *%a2
|
|
%2 = shl i64 %a0, %a1
|
|
%3 = shl i64 %1, %a1
|
|
%4 = add i64 %2, %3
|
|
ret i64 %4
|
|
}
|
|
|
|
define i32 @test_shrx_i32(i32 %a0, i32 %a1, i32 *%a2) {
|
|
; GENERIC-LABEL: test_shrx_i32:
|
|
; GENERIC: # BB#0:
|
|
; GENERIC-NEXT: shrxl %esi, %edi, %ecx # sched: [1:0.50]
|
|
; GENERIC-NEXT: shrxl %esi, (%rdx), %eax # sched: [5:0.50]
|
|
; GENERIC-NEXT: addl %ecx, %eax # sched: [1:0.33]
|
|
; GENERIC-NEXT: retq # sched: [1:1.00]
|
|
;
|
|
; HASWELL-LABEL: test_shrx_i32:
|
|
; HASWELL: # BB#0:
|
|
; HASWELL-NEXT: shrxl %esi, %edi, %ecx # sched: [1:0.50]
|
|
; HASWELL-NEXT: shrxl %esi, (%rdx), %eax # sched: [5:0.50]
|
|
; HASWELL-NEXT: addl %ecx, %eax # sched: [1:0.25]
|
|
; HASWELL-NEXT: retq # sched: [1:1.00]
|
|
;
|
|
; ZNVER1-LABEL: test_shrx_i32:
|
|
; ZNVER1: # BB#0:
|
|
; ZNVER1-NEXT: shrxl %esi, (%rdx), %eax # sched: [5:0.50]
|
|
; ZNVER1-NEXT: shrxl %esi, %edi, %ecx # sched: [1:0.25]
|
|
; ZNVER1-NEXT: addl %ecx, %eax # sched: [1:0.25]
|
|
; ZNVER1-NEXT: retq # sched: [5:0.50]
|
|
%1 = load i32, i32 *%a2
|
|
%2 = lshr i32 %a0, %a1
|
|
%3 = lshr i32 %1, %a1
|
|
%4 = add i32 %2, %3
|
|
ret i32 %4
|
|
}
|
|
|
|
define i64 @test_shrx_i64(i64 %a0, i64 %a1, i64 *%a2) {
|
|
; GENERIC-LABEL: test_shrx_i64:
|
|
; GENERIC: # BB#0:
|
|
; GENERIC-NEXT: shrxq %rsi, %rdi, %rcx # sched: [1:0.50]
|
|
; GENERIC-NEXT: shrxq %rsi, (%rdx), %rax # sched: [5:0.50]
|
|
; GENERIC-NEXT: addq %rcx, %rax # sched: [1:0.33]
|
|
; GENERIC-NEXT: retq # sched: [1:1.00]
|
|
;
|
|
; HASWELL-LABEL: test_shrx_i64:
|
|
; HASWELL: # BB#0:
|
|
; HASWELL-NEXT: shrxq %rsi, %rdi, %rcx # sched: [1:0.50]
|
|
; HASWELL-NEXT: shrxq %rsi, (%rdx), %rax # sched: [5:0.50]
|
|
; HASWELL-NEXT: addq %rcx, %rax # sched: [1:0.25]
|
|
; HASWELL-NEXT: retq # sched: [1:1.00]
|
|
;
|
|
; ZNVER1-LABEL: test_shrx_i64:
|
|
; ZNVER1: # BB#0:
|
|
; ZNVER1-NEXT: shrxq %rsi, (%rdx), %rax # sched: [5:0.50]
|
|
; ZNVER1-NEXT: shrxq %rsi, %rdi, %rcx # sched: [1:0.25]
|
|
; ZNVER1-NEXT: addq %rcx, %rax # sched: [1:0.25]
|
|
; ZNVER1-NEXT: retq # sched: [5:0.50]
|
|
%1 = load i64, i64 *%a2
|
|
%2 = lshr i64 %a0, %a1
|
|
%3 = lshr i64 %1, %a1
|
|
%4 = add i64 %2, %3
|
|
ret i64 %4
|
|
}
|