forked from OSchip/llvm-project
120 lines
2.7 KiB
YAML
120 lines
2.7 KiB
YAML
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+sse2 -global-isel -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=SSE2
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--- |
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define void @test_add_v16i8() {
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%ret = add <16 x i8> undef, undef
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ret void
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}
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define void @test_add_v8i16() {
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%ret = add <8 x i16> undef, undef
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ret void
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}
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define void @test_add_v4i32() {
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%ret = add <4 x i32> undef, undef
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ret void
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}
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define void @test_add_v2i64() {
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%ret = add <2 x i64> undef, undef
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ret void
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}
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...
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---
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name: test_add_v16i8
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# ALL-LABEL: name: test_add_v16i8
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alignment: 4
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legalized: false
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regBankSelected: false
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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# ALL: %0(<16 x s8>) = IMPLICIT_DEF
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# ALL-NEXT: %1(<16 x s8>) = IMPLICIT_DEF
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# ALL-NEXT: %2(<16 x s8>) = G_ADD %0, %1
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# ALL-NEXT: RET 0
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body: |
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bb.1 (%ir-block.0):
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liveins: %xmm0, %xmm1
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%0(<16 x s8>) = IMPLICIT_DEF
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%1(<16 x s8>) = IMPLICIT_DEF
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%2(<16 x s8>) = G_ADD %0, %1
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RET 0
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...
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---
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name: test_add_v8i16
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# ALL-LABEL: name: test_add_v8i16
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alignment: 4
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legalized: false
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regBankSelected: false
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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# ALL: %0(<8 x s16>) = IMPLICIT_DEF
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# ALL-NEXT: %1(<8 x s16>) = IMPLICIT_DEF
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# ALL-NEXT: %2(<8 x s16>) = G_ADD %0, %1
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# ALL-NEXT: RET 0
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body: |
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bb.1 (%ir-block.0):
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liveins: %xmm0, %xmm1
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%0(<8 x s16>) = IMPLICIT_DEF
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%1(<8 x s16>) = IMPLICIT_DEF
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%2(<8 x s16>) = G_ADD %0, %1
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RET 0
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...
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---
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name: test_add_v4i32
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# ALL-LABEL: name: test_add_v4i32
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alignment: 4
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legalized: false
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regBankSelected: false
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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# ALL: %0(<4 x s32>) = IMPLICIT_DEF
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# ALL-NEXT: %1(<4 x s32>) = IMPLICIT_DEF
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# ALL-NEXT: %2(<4 x s32>) = G_ADD %0, %1
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# ALL-NEXT: RET 0
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body: |
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bb.1 (%ir-block.0):
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liveins: %xmm0, %xmm1
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%0(<4 x s32>) = IMPLICIT_DEF
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%1(<4 x s32>) = IMPLICIT_DEF
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%2(<4 x s32>) = G_ADD %0, %1
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RET 0
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...
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---
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name: test_add_v2i64
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# ALL-LABEL: name: test_add_v2i64
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alignment: 4
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legalized: false
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regBankSelected: false
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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# ALL: %0(<2 x s64>) = IMPLICIT_DEF
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# ALL-NEXT: %1(<2 x s64>) = IMPLICIT_DEF
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# ALL-NEXT: %2(<2 x s64>) = G_ADD %0, %1
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# ALL-NEXT: RET 0
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body: |
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bb.1 (%ir-block.0):
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liveins: %xmm0, %xmm1
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%0(<2 x s64>) = IMPLICIT_DEF
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%1(<2 x s64>) = IMPLICIT_DEF
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%2(<2 x s64>) = G_ADD %0, %1
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RET 0
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...
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