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AArch64
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AArch64/GlobalISel: Remove IR section from test
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2021-03-28 11:12:59 -04:00 |
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AMDGPU
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[AMDGPU] Extend gfx10 test coverage. NFC.
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2021-03-29 11:13:55 +02:00 |
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ARC
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…
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ARM
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[ARM] MVE vector lane interleaving
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2021-03-28 19:34:58 +01:00 |
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AVR
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[AVR] Fix lifeness issues in the AVR backend
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2021-03-04 14:04:39 +01:00 |
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BPF
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BPF: add extern func to data sections if specified
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2021-03-25 16:03:29 -07:00 |
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Generic
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[XCore][Test] XFAIL tests requiring 8-byte stack alignment.
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2021-03-24 09:12:53 +00:00 |
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Hexagon
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[Hexagon] Add support for named registers cs0 and cs1
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2021-03-18 09:53:22 -05:00 |
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Inputs
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…
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Lanai
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…
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M68k
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[DAG] computeKnownBits - add ISD::MULHS/MULHU/SMUL_LOHI/UMUL_LOHI handling
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2021-03-19 16:02:31 +00:00 |
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MIR
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MIR: Fix missing serialization for HasTailCall
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2021-03-21 13:14:04 -04:00 |
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MSP430
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…
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Mips
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Test cases for rem-seteq fold with illegal types
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2021-03-12 16:28:04 +02:00 |
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NVPTX
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[NVPTX] CUDA does provide malloc/free since compute capability 2.X
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2021-03-15 22:45:56 -05:00 |
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PowerPC
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[PowerPC] auto-generate complete testchecks; NFC
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2021-03-25 15:52:39 -04:00 |
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RISCV
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[RISCV] Add a RV64 mulhsu test case. NFC
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2021-03-28 15:54:44 -07:00 |
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SPARC
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[LegalizeTypes] Improve ExpandIntRes_XMULO codegen.
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2021-03-01 09:54:32 -08:00 |
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SystemZ
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[SystemZ] Reimplement the i8/i16 compare-and-swap logic.
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2021-03-03 14:04:32 -06:00 |
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Thumb
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[ARM] Regenerate some test checks. NFC
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2021-03-24 15:34:34 +00:00 |
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Thumb2
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[ARM] Extend MVE lane interleaving to handle other non-instruction leaves
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2021-03-29 09:05:45 +01:00 |
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VE
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[test] Fix CodeGen/VE/Scalar tests
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2021-03-02 15:30:44 -08:00 |
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WebAssembly
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[WebAssembly] Rename WasmLimits::Initial to ::Minimum. NFC.
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2021-03-24 09:10:11 +01:00 |
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WinCFGuard
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…
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WinEH
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…
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X86
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Reapply "OpaquePtr: Turn inalloca into a type attribute"
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2021-03-29 08:55:30 -04:00 |
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XCore
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[CodeGen] Report a normal instead of fatal error for label redefinition
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2021-03-09 10:54:41 +00:00 |
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