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Zvi Rackover 72b0bb1405 X86 Tests: Update more isel tests with FastVariableShuffle feature 
Summary:
Added the FastVariableShuffle feature to cases that resembled processors
for which this fearure is on.
For AVX2 there are processors with and w/o this fearue enable.
For AVX512 only KNL does enable this feature so cases which only have
+avx512f were left without the FastVariableShuffle enabled.

Reviewers: RKSimon, craig.topper

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D41851

llvm-svn: 322090
 		2018-01-09 16:26:06 +00:00
..
AArch64 [CodeGen] Print frame-setup/destroy flags in -debug output like we do in MIR 2018-01-09 16:11:51 +00:00
AMDGPU [CodeGen] Don't print register classes in -debug output 2018-01-09 15:39:44 +00:00
ARC
…
ARM [CodeGen] Don't print register classes in -debug output 2018-01-09 15:39:44 +00:00
AVR [AVR] Fix two CodeGen tests 2017-12-09 07:51:43 +00:00
BPF bpf: add support for objdump -print-imm-hex 2017-12-20 19:39:58 +00:00
Generic [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
Hexagon [Hexagon] Even simpler patterns for sign- and zero-extending HVX vectors 2018-01-05 22:31:11 +00:00
Inputs
…
Lanai [CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register. 2017-12-07 10:40:31 +00:00
MIR [MIR] Add support for the frame-destroy MachineInstr flag 2018-01-09 11:33:22 +00:00
MSP430 [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
Mips [mips] Replace assert by an error message 2017-12-29 19:18:24 +00:00
NVPTX [DEBUG] Add initial tests for debug info for NVPTX target, NFC. 2018-01-04 21:07:07 +00:00
Nios2 [Nios2] Arithmetic instructions for R1 and R2 ISA. 2018-01-09 11:15:08 +00:00
PowerPC [CodeGen] Don't print register classes in -debug output 2018-01-09 15:39:44 +00:00
RISCV [RISCV] Enable emission of alias instructions by default 2017-12-15 09:47:01 +00:00
SPARC Revert r318704 - [Sparc] efficient pattern for UINT_TO_FP conversion 2017-12-11 22:25:04 +00:00
SystemZ [MachineOperand][MIR] Add isRenamable to MachineOperand. 2017-12-12 17:53:59 +00:00
Thumb [ARM] Fix PR35481 2018-01-08 11:32:37 +00:00
Thumb2 [ARM] Register the Thumb2SizeReducePass. NFC 2017-12-19 12:19:08 +00:00
WebAssembly [WebAssembly] Implement @llvm.global_ctors and @llvm.global_dtors 2017-12-15 00:17:10 +00:00
WinEH
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X86 X86 Tests: Update more isel tests with FastVariableShuffle feature 2018-01-09 16:26:06 +00:00
XCore
…