Eli Friedman ddf5e86c22 [ARM] VFPv2 only supports 16 D registers. ... r361845 changed the way we handle "D16" vs. "D32" targets; there used to be a negative "d16" which removed instructions from the instruction set, and now there's a "d32" feature which adds instructions to the instruction set. This is good, but there was an oversight in the implementation: the behavior of VFPv2 was changed. In particular, the "vfp2" feature was changed to imply "d32". This is wrong: VFPv2 only supports 16 D registers. In practice, this means if you specify -mfpu=vfpv2, the compiler will generate illegal instructions. This patch gets rid of "vfp2d16" and "vfp2d16sp", and fixes "vfp2" and "vfp2sp" so they don't imply "d32". Differential Revision: https://reviews.llvm.org/D67375 llvm-svn: 372186		2019-09-17 21:42:38 +00:00
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arm-call-lowering.ll	…
arm-instruction-select-cmp.mir	…
arm-instruction-select-combos.mir	…
arm-instruction-select.mir	[ARM GlobalISel] Select extensions to < 32 bits	2019-05-02 09:28:00 +00:00
arm-irtranslator.ll	[GlobalISel] CSEMIRBuilder: Add support for G_GEP	2019-08-15 23:45:45 +00:00
arm-isel-divmod.ll	…
arm-isel-fp.ll	…
arm-isel-globals-pic.ll	…
arm-isel-globals-ropi-rwpi.ll	…
arm-isel-globals-static.ll	…
arm-isel.ll	…
arm-legalize-binops-neon.mir	[ARM GlobalISel] Tests for s64 G_ADD and G_SUB.	2019-06-20 22:00:07 +00:00
arm-legalize-binops.mir	[ARM GlobalISel] Widen small shift operands	2019-04-30 09:24:43 +00:00
arm-legalize-bitcounts.mir	[GlobalISel] Enable CSE in the IRTranslator & legalizer for -O0 with constants only.	2019-04-15 05:04:20 +00:00
arm-legalize-casts.mir	[ARM GlobalISel] Widen G_INTTOPTR/G_PTRTOINT	2019-05-07 10:48:01 +00:00
arm-legalize-cmp.mir	…
arm-legalize-consts.mir	…
arm-legalize-control-flow.mir	…
arm-legalize-divmod.mir	[globalisel] Add G_SEXT_INREG	2019-08-09 21:11:20 +00:00
arm-legalize-exts.mir	[globalisel] Add G_SEXT_INREG	2019-08-09 21:11:20 +00:00
arm-legalize-fp.mir	[GlobalISel] Enable CSE in the IRTranslator & legalizer for -O0 with constants only.	2019-04-15 05:04:20 +00:00
arm-legalize-globals.mir	…
arm-legalize-load-store.mir	[ARM] VFPv2 only supports 16 D registers.	2019-09-17 21:42:38 +00:00
arm-legalize-select.mir	[ARM GlobalISel] Widen G_SELECT operands	2019-05-07 11:39:30 +00:00
arm-legalize-vfp4.mir	…
arm-legalizer.mir	…
arm-param-lowering.ll	[GlobalISel] Accept multiple vregs for lowerCall's args	2019-06-27 09:18:03 +00:00
arm-regbankselect.mir	[ARM GlobalISel] Map DBG_VALUE for types != s32	2019-05-09 09:49:36 +00:00
arm-select-copy_to_regclass-of-fptosi.mir	…
arm-select-globals-pic.mir	…
arm-select-globals-ropi-rwpi.mir	…
arm-select-globals-static.mir	…
arm-unsupported.ll	[ARM GlobalISel] Be more careful about bailing out	2019-04-30 09:05:25 +00:00
irtranslator-varargs-lowering.ll	…
lit.local.cfg	…
pr35375.ll	Rename ExpandISelPseudo->FinalizeISel, delay register reservation	2019-06-19 00:25:39 +00:00
select-clz.mir	…
select-dbg.mir	[ARM GlobalISel] Support DBG_VALUE	2019-04-04 10:24:51 +00:00
select-fp-const.mir	[ARM GlobalISel] Select G_FCONSTANT for VFP3	2019-04-10 09:14:32 +00:00
select-fp.mir	…
select-neon.mir	[ARM GlobalISel] Tests for s64 G_ADD and G_SUB.	2019-06-20 22:00:07 +00:00
select-pkhbt.mir	…
select-pr35926.mir	…
select-revsh.mir	…
thumb-instruction-select-cmp.mir	…
thumb-isel-globals-pic.ll	…
thumb-isel-globals-ropi-rwpi.ll	…
thumb-isel-globals-static.ll	…
thumb-select-arithmetic-ops.mir	…
thumb-select-br.mir	ARM: disallow SP as Rn for Thumb2 TST & TEQ instructions	2019-05-08 10:59:08 +00:00
thumb-select-casts.mir	…
thumb-select-exts.mir	[ARM GlobalISel] Select extensions to < 32 bits	2019-05-02 09:28:00 +00:00
thumb-select-globals-pic.mir	…
thumb-select-globals-ropi-rwpi.mir	…
thumb-select-globals-static.mir	…
thumb-select-imm.mir	…
thumb-select-load-store.mir	[ARM GlobalISel] Fix G_STORE with s1	2019-03-28 09:09:36 +00:00
thumb-select-logical-ops.mir	…
thumb-select-phi.mir	…
thumb-select-select.mir	ARM: disallow SP as Rn for Thumb2 TST & TEQ instructions	2019-05-08 10:59:08 +00:00
thumb-select-shifts.mir	…