forked from OSchip/llvm-project
35 lines
664 B
TableGen
35 lines
664 B
TableGen
// RUN: llvm-tblgen %s | FileCheck %s
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// XFAIL: vg_leak
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// CHECK: bit IsDouble = 1;
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// CHECK: bit IsDouble = 1;
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// CHECK: bit IsDouble = 1;
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// CHECK-NOT: bit IsDouble = 1;
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class Instruction<bits<4> opc, string Name> {
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bits<4> opcode = opc;
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string name = Name;
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bit IsDouble = 0;
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}
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multiclass basic_r<bits<4> opc> {
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let name = "newname" in {
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def rr : Instruction<opc, "rr">;
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def rm : Instruction<opc, "rm">;
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}
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let name = "othername" in
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def rx : Instruction<opc, "rx">;
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}
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multiclass basic_ss<bits<4> opc> {
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let IsDouble = 0 in
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defm SS : basic_r<opc>;
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let IsDouble = 1 in
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defm SD : basic_r<opc>;
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}
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defm ADD : basic_ss<0xf>;
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