Stanislav Mekhanoshin 46a75436f8 [AMDGPU] Define special SGPR subregs ... These are used in SReg_32 and when we start to use SGPR_LO16 there will be compaints that not all registers in RC support all subreg indexes. For now it is NFC. Unused regunits are reserved so that verifier does not complain about missing phys reg live-ins. Differential Revision: https://reviews.llvm.org/D78591		2020-04-28 14:57:46 -07:00
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AArch64	[GlobalISel] Assign the correct debug location when combining G_ANYEXT/G_ZEXT	2020-04-28 14:12:33 -07:00
AMDGPU	[AMDGPU] Define special SGPR subregs	2020-04-28 14:57:46 -07:00
ARC	…
ARM	[AsmPrinter] Fix emission of non-standard integer constants for BE targets	2020-04-27 14:57:29 -07:00
AVR	[AVR] Do not place functions in .progmem.data	2020-04-20 13:56:38 +02:00
BPF	BPF: fix a CORE optimization bug	2020-04-20 19:54:51 -07:00
Generic	[MachineDebugify] Insert synthetic DBG_VALUE instructions	2020-04-22 17:03:39 -07:00
Hexagon	Handle part-word LL/SC in atomic expansion pass	2020-04-28 10:07:39 -05:00
Inputs	…
Lanai	…
MIR	[AMDGPU] Avoid hard-coded line numbers in error message checks	2020-04-23 21:06:09 +01:00
MSP430	…
Mips	[AsmPrinter] Fix emission of non-standard integer constants for BE targets	2020-04-27 14:57:29 -07:00
NVPTX	[llvm] Fix missing FileCheck directive colons	2020-04-06 09:59:08 -06:00
PowerPC	[PowerPC][AIX] Pass ByVal formal args that span registers and stack.	2020-04-28 14:57:14 -04:00
RISCV	[RISCV][AsmParser] Implement .option (no)pic	2020-04-17 12:08:30 +00:00
SPARC	…
SystemZ	[SystemZ] Fix test case.	2020-04-28 09:43:03 +02:00
Thumb	[ARM] Don't shrink STM if it would cause an unknown base register store	2020-04-22 14:50:42 +01:00
Thumb2	[ARM] Always replace FP16 bitcasts with VMOVhr or VMOVrh	2020-04-28 16:12:53 +01:00
VE	[VE] Update branch instructions	2020-04-28 09:41:01 +02:00
WebAssembly	[WebAssembly] Add int32 DW_OP_WASM_location variant	2020-04-16 16:32:17 -07:00
WinCFGuard	…
WinEH	…
X86	[X86] Handle more cases in combineAddOrSubToADCOrSBB.	2020-04-28 10:39:39 -07:00
XCore	…