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llvm-project/llvm/lib/Target/AArch64
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Reid Kleckner 2d89e0a098 [SEH] Remove CATCHPAD SDNode and X86::EH_RESTORE MachineInstr 
The CATCHPAD node mostly existed to be selected into the EH_RESTORE
instruction, which sets the frame back up when 32-bit Windows exceptions
return to the parent function. However, creating this MachineInstr early
increases the risk that other passes will come along and insert
instructions that use the stack before ESP and EBP are restored. That
happened in PR44697.

Instead of representing these in the instruction stream early, delay it
until PEI. Mark the blocks where this needs to happen as EHPads, but not
funclet entry blocks. Passes after PEI have to be careful not to hoist
instructions that can use stack across frame setup instructions, so this
should be relatively reliable.

Fixes PR44697

Reviewed By: hans

Differential Revision: https://reviews.llvm.org/D73752
 		2020-02-04 15:13:12 -08:00
..
AsmParser [AArch64] Add IR intrinsics for sq(r)dmulh_lane(q) 2020-01-29 13:25:23 +00:00
Disassembler CMake: Make most target symbols hidden by default 2020-01-14 19:46:52 -08:00
MCTargetDesc CMake: Make most target symbols hidden by default 2020-01-14 19:46:52 -08:00
TargetInfo CMake: Make most target symbols hidden by default 2020-01-14 19:46:52 -08:00
Utils [AArch64][SVE] Add patterns for unpredicated load/store to frame-indices. 2020-01-22 14:32:27 +00:00
AArch64.h GlobalISel: add combiner to form indexed loads. 2019-09-09 10:04:23 +00:00
AArch64.td AArch64: add missing Apple CPU names and use them by default. 2020-01-08 09:24:06 +00:00
AArch64A53Fix835769.cpp
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AArch64A57FPLoadBalancing.cpp [llvm] Migrate llvm::make_unique to std::make_unique 2019-08-15 15:54:37 +00:00
AArch64AdvSIMDScalarPass.cpp [aarch64] Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM 2019-08-12 22:40:53 +00:00
AArch64AsmPrinter.cpp [AArch64] -fpatchable-function-entry=N,0: place patch label after BTI 2020-01-30 11:11:52 -08:00
AArch64BranchTargets.cpp
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AArch64CallLowering.cpp [GlobalISel] Tidy up unnecessary calls to createGenericVirtualRegister 2020-01-31 17:07:16 +00:00
AArch64CallLowering.h [AArch64][GlobalISel][NFC] Refactor tail call lowering code 2019-09-17 19:08:44 +00:00
AArch64CallingConvention.cpp [Alignment][NFC] Remove unneeded llvm:: scoping on Align types 2019-09-27 12:54:21 +00:00
AArch64CallingConvention.h Add Windows Control Flow Guard checks (/guard:cf). 2019-10-28 15:19:39 +00:00
AArch64CallingConvention.td [AArch64][SVE] Remove nxv1f32 and nxv1f64 as legal types 2019-12-12 09:49:22 +00:00
AArch64CleanupLocalDynamicTLSPass.cpp
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AArch64CollectLOH.cpp AArch64: support arm64_32, an ILP32 slice for watchOS. 2019-09-12 10:22:23 +00:00
AArch64Combine.td [AArch64][GlobalISel] Change G_FCONSTANTs feeding into stores into G_CONSTANTS 2020-01-16 15:18:44 -08:00
AArch64CompressJumpTables.cpp [Alignment][NFC] Deprecate Align::None() 2020-01-24 12:53:58 +01:00
AArch64CondBrTuning.cpp [aarch64] Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM 2019-08-12 22:40:53 +00:00
AArch64ConditionOptimizer.cpp Update spelling of {analyze,insert,remove}Branch in strings and comments 2020-01-21 10:15:38 -06:00
AArch64ConditionalCompares.cpp Update spelling of {analyze,insert,remove}Branch in strings and comments 2020-01-21 10:15:38 -06:00
AArch64DeadRegisterDefinitionsPass.cpp [aarch64] Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM 2019-08-12 22:40:53 +00:00
AArch64ExpandImm.cpp
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AArch64ExpandImm.h
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AArch64ExpandPseudoInsts.cpp [Fuchsia] Remove aarch64-fuchsia target-specific -mcmodel=kernel 2020-01-28 11:32:08 -08:00
AArch64FalkorHWPFFix.cpp [TargetRegisterInfo] Default trackLivenessAfterRegAlloc() to true 2020-01-19 14:20:37 -08:00
AArch64FastISel.cpp [AArch64] [Windows] Use COFF stubs for calls to extern_weak functions 2019-12-23 12:13:49 +02:00
AArch64FrameLowering.cpp Merge memtag instructions with adjacent stack slots. 2020-01-17 15:19:29 -08:00
AArch64FrameLowering.h Merge memtag instructions with adjacent stack slots. 2020-01-17 15:19:29 -08:00
AArch64GenRegisterBankInfo.def
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AArch64ISelDAGToDAG.cpp [AArch64][SVE] Add patterns for unpredicated load/store to frame-indices. 2020-01-22 14:32:27 +00:00
AArch64ISelLowering.cpp [SEH] Remove CATCHPAD SDNode and X86::EH_RESTORE MachineInstr 2020-02-04 15:13:12 -08:00
AArch64ISelLowering.h [SEH] Remove CATCHPAD SDNode and X86::EH_RESTORE MachineInstr 2020-02-04 15:13:12 -08:00
AArch64InstrAtomics.td DAG: Use TargetConstant for FENCE operands 2020-01-02 17:16:10 -05:00
AArch64InstrFormats.td [AArch64][SVE] Add remaining SVE2 intrinsics for uniform DSP operations 2020-01-31 10:51:57 +00:00
AArch64InstrInfo.cpp [NFC] unsigned->Register in storeRegTo/loadRegFromStack 2020-02-03 14:22:16 +01:00
AArch64InstrInfo.h [NFC] unsigned->Register in storeRegTo/loadRegFromStack 2020-02-03 14:22:16 +01:00
AArch64InstrInfo.td [SEH] Remove CATCHPAD SDNode and X86::EH_RESTORE MachineInstr 2020-02-04 15:13:12 -08:00
AArch64InstructionSelector.cpp [AArch64][GlobalISel] Fold G_XOR into TB(N)Z bit calculation 2020-02-03 15:22:24 -08:00
AArch64LegalizerInfo.cpp [GlobalISel] Tidy up unnecessary calls to createGenericVirtualRegister 2020-01-31 17:07:16 +00:00
AArch64LegalizerInfo.h GlobalISel: Add observer argument to legalizeIntrinsic 2020-01-29 18:33:45 -05:00
AArch64LoadStoreOptimizer.cpp [AArch64] Add option to enable/disable load-store renaming. 2020-01-27 15:15:50 -08:00
AArch64MCInstLower.cpp AArch64: Add a tagged-globals backend feature. 2019-07-31 20:14:19 +00:00
AArch64MCInstLower.h
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AArch64MachineFunctionInfo.h Revert "AArch64: Fix frame record chain" 2019-12-14 13:58:40 -08:00
AArch64MacroFusion.cpp
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AArch64MacroFusion.h
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AArch64PBQPRegAlloc.cpp [aarch64] Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM 2019-08-12 22:40:53 +00:00
AArch64PBQPRegAlloc.h
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AArch64PerfectShuffle.h
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AArch64PfmCounters.td
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AArch64PreLegalizerCombiner.cpp [AArch64][GlobalISel] Change G_FCONSTANTs feeding into stores into G_CONSTANTS 2020-01-16 15:18:44 -08:00
AArch64PromoteConstant.cpp Sink all InitializePasses.h includes 2019-11-13 16:34:37 -08:00
AArch64RedundantCopyElimination.cpp
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AArch64RegisterBankInfo.cpp Revert "Reland "[AArch64] Fix data race on RegisterBank initialization."" 2020-02-03 16:58:58 -08:00
AArch64RegisterBankInfo.h GlobalISel: Add type argument to getRegBankFromRegClass 2020-01-03 16:25:10 -05:00
AArch64RegisterBanks.td
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AArch64RegisterInfo.cpp [AArch64] Add IR intrinsics for sq(r)dmulh_lane(q) 2020-01-29 13:25:23 +00:00
AArch64RegisterInfo.h [TargetRegisterInfo] Default trackLivenessAfterRegAlloc() to true 2020-01-19 14:20:37 -08:00
AArch64RegisterInfo.td [AArch64] Add IR intrinsics for sq(r)dmulh_lane(q) 2020-01-29 13:25:23 +00:00
AArch64SIMDInstrOpt.cpp Make llvm::StringRef to std::string conversions explicit. 2020-01-28 23:25:25 +01:00
AArch64SVEInstrInfo.td [AArch64][SVE] Add SVE2 mla unpredicated intrinsics. 2020-01-31 11:39:12 -05:00
AArch64SchedA53.td
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AArch64SchedA57.td
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AArch64SchedA57WriteRes.td
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AArch64SchedCyclone.td
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AArch64SchedExynosM3.td [AArch64] Update for Exynos 2019-11-12 14:37:41 -06:00
AArch64SchedExynosM4.td [AArch64] Update for Exynos 2019-11-12 14:37:41 -06:00
AArch64SchedExynosM5.td [AArch64] Add the pipeline model for Exynos M5 2019-11-22 15:09:17 -06:00
AArch64SchedFalkor.td
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AArch64SchedFalkorDetails.td
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AArch64SchedKryo.td
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AArch64SchedKryoDetails.td
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AArch64SchedPredExynos.td [AArch64] Add new scheduling predicates 2019-11-11 15:02:51 -06:00
AArch64SchedPredicates.td [NFC] [AArch64] Fix wrong documentation for IsStoreRegOffsetOp 2019-11-23 19:11:31 +01:00
AArch64SchedThunderX.td
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AArch64SchedThunderX2T99.td [AArch64] Remove overlapping scheduling definitions (NFC) 2019-10-30 13:57:27 -05:00
AArch64Schedule.td
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AArch64SelectionDAGInfo.cpp Merge memtag instructions with adjacent stack slots. 2020-01-17 15:19:29 -08:00
AArch64SelectionDAGInfo.h Basic codegen for MTE stack tagging. 2019-07-17 19:24:02 +00:00
AArch64SpeculationHardening.cpp Prune a LegacyDivergenceAnalysis and MachineLoopInfo include each 2019-10-19 01:31:09 +00:00
AArch64StackOffset.h [SVE][CodeGen] Scalable vector MVT size queries 2019-11-18 12:30:59 +00:00
AArch64StackTagging.cpp [IR] Split out target specific intrinsic enums into separate headers 2019-12-11 18:02:14 -08:00
AArch64StackTaggingPreRA.cpp MTE: add more unchecked instructions. 2019-11-19 11:19:53 -08:00
AArch64StorePairSuppress.cpp [aarch64] Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM 2019-08-12 22:40:53 +00:00
AArch64Subtarget.cpp AArch64: add missing Apple CPU names and use them by default. 2020-01-08 09:24:06 +00:00
AArch64Subtarget.h AArch64: add missing Apple CPU names and use them by default. 2020-01-08 09:24:06 +00:00
AArch64SystemOperands.td AArch64: add missing Apple CPU names and use them by default. 2020-01-08 09:24:06 +00:00
AArch64TargetMachine.cpp [Fuchsia] Remove aarch64-fuchsia target-specific -mcmodel=kernel 2020-01-28 11:32:08 -08:00
AArch64TargetMachine.h
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AArch64TargetObjectFile.cpp Revert "Honor -fuse-init-array when os is not specified on x86" 2019-12-17 07:36:59 -08:00
AArch64TargetObjectFile.h [MachO][TLOF] Use hasLocalLinkage to determine if indirect symbol is local 2019-08-22 16:59:00 +00:00
AArch64TargetTransformInfo.cpp [IR] Split out target specific intrinsic enums into separate headers 2019-12-11 18:02:14 -08:00
AArch64TargetTransformInfo.h [AArch64][ARM] Always expand ordered vector reductions (PR44600) 2020-01-30 18:40:24 +01:00
CMakeLists.txt [gicombiner] Fix windows issue where single quotes in the command are passed through to tablegen 2019-10-02 23:38:06 +00:00
LLVMBuild.txt Add Windows Control Flow Guard checks (/guard:cf). 2019-10-28 15:19:39 +00:00
SVEInstrFormats.td [AArch64][SVE] Add SVE2 mla unpredicated intrinsics. 2020-01-31 11:39:12 -05:00