forked from OSchip/llvm-project
81 lines
2.0 KiB
LLVM
81 lines
2.0 KiB
LLVM
; RUN: llc -march=hexagon -mcpu=hexagonv4 -O3 < %s | FileCheck %s
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; Check that the combine/stxw instructions are being generated.
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; In case of combine one of the operand should be 0 and another should be
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; the output of absolute addressing load instruction.
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@a = external global i16
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@b = external global i16
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@c = external global i16
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@char_a = external global i8
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@char_b = external global i8
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@char_c = external global i8
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@int_a = external global i32
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@int_b = external global i32
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@int_c = external global i32
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; Function Attrs: nounwind
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define i64 @short_test1() #0 {
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; CHECK: [[VAR:r[0-9]+]]{{ *}}={{ *}}memuh(##
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; CHECK: combine(#0, [[VAR]])
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entry:
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store i16 0, i16* @a, align 2
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%0 = load i16* @b, align 2
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%conv2 = zext i16 %0 to i64
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ret i64 %conv2
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}
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; Function Attrs: nounwind
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define i64 @short_test2() #0 {
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; CHECK: [[VAR1:r[0-9]+]]{{ *}}={{ *}}memh(##
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; CHECK: sxtw([[VAR1]])
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entry:
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store i16 0, i16* @a, align 2
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%0 = load i16* @c, align 2
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%conv2 = sext i16 %0 to i64
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ret i64 %conv2
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}
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; Function Attrs: nounwind
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define i64 @char_test1() #0 {
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; CHECK: [[VAR2:r[0-9]+]]{{ *}}={{ *}}memub(##
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; CHECK: combine(#0, [[VAR2]])
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entry:
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store i8 0, i8* @char_a, align 1
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%0 = load i8* @char_b, align 1
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%conv2 = zext i8 %0 to i64
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ret i64 %conv2
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}
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; Function Attrs: nounwind
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define i64 @char_test2() #0 {
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; CHECK: [[VAR3:r[0-9]+]]{{ *}}={{ *}}memb(##
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; CHECK: sxtw([[VAR3]])
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entry:
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store i8 0, i8* @char_a, align 1
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%0 = load i8* @char_c, align 1
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%conv2 = sext i8 %0 to i64
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ret i64 %conv2
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}
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; Function Attrs: nounwind
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define i64 @int_test1() #0 {
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; CHECK: [[VAR4:r[0-9]+]]{{ *}}={{ *}}memw(##
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; CHECK: combine(#0, [[VAR4]])
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entry:
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store i32 0, i32* @int_a, align 4
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%0 = load i32* @int_b, align 4
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%conv = zext i32 %0 to i64
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ret i64 %conv
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}
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; Function Attrs: nounwind
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define i64 @int_test2() #0 {
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; CHECK: [[VAR5:r[0-9]+]]{{ *}}={{ *}}memw(##
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; CHECK: sxtw([[VAR5]])
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entry:
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store i32 0, i32* @int_a, align 4
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%0 = load i32* @int_c, align 4
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%conv = sext i32 %0 to i64
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ret i64 %conv
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}
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