forked from OSchip/llvm-project
47 lines
1.1 KiB
LLVM
47 lines
1.1 KiB
LLVM
; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
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; Check that we generate load instructions with absolute addressing mode.
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@a = external global i32
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@b = external global i8
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@c = external global i16
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@d = external global i64
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define zeroext i8 @absStoreByte() nounwind {
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; CHECK: memb(##b){{ *}}={{ *}}r{{[0-9]+}}
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entry:
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%0 = load i8* @b, align 1
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%conv = zext i8 %0 to i32
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%mul = mul nsw i32 100, %conv
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%conv1 = trunc i32 %mul to i8
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store i8 %conv1, i8* @b, align 1
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ret i8 %conv1
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}
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define signext i16 @absStoreHalf() nounwind {
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; CHECK: memh(##c){{ *}}={{ *}}r{{[0-9]+}}
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entry:
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%0 = load i16* @c, align 2
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%conv = sext i16 %0 to i32
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%mul = mul nsw i32 100, %conv
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%conv1 = trunc i32 %mul to i16
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store i16 %conv1, i16* @c, align 2
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ret i16 %conv1
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}
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define i32 @absStoreWord() nounwind {
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; CHECK: memw(##a){{ *}}={{ *}}r{{[0-9]+}}
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entry:
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%0 = load i32* @a, align 4
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%mul = mul nsw i32 100, %0
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store i32 %mul, i32* @a, align 4
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ret i32 %mul
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}
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define void @absStoreDouble() nounwind {
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; CHECK: memd(##d){{ *}}={{ *}}r{{[0-9]+}}:{{[0-9]+}}
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entry:
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store i64 100, i64* @d, align 8
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ret void
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}
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