forked from OSchip/llvm-project
239 lines
7.1 KiB
YAML
239 lines
7.1 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=aarch64-- -mattr=+lse -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
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--- |
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target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
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define void @atomicrmw_xchg_i64(i64* %addr) { ret void }
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define void @atomicrmw_add_i64(i64* %addr) { ret void }
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define void @atomicrmw_add_i32(i64* %addr) { ret void }
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define void @atomicrmw_sub_i32(i64* %addr) { ret void }
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define void @atomicrmw_and_i32(i64* %addr) { ret void }
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; nand isn't legal
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define void @atomicrmw_or_i32(i64* %addr) { ret void }
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define void @atomicrmw_xor_i32(i64* %addr) { ret void }
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define void @atomicrmw_min_i32(i64* %addr) { ret void }
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define void @atomicrmw_max_i32(i64* %addr) { ret void }
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define void @atomicrmw_umin_i32(i64* %addr) { ret void }
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define void @atomicrmw_umax_i32(i64* %addr) { ret void }
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...
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---
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name: atomicrmw_xchg_i64
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: atomicrmw_xchg_i64
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; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK: [[CST:%[0-9]+]]:gpr64 = MOVi64imm 1
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; CHECK: [[RES:%[0-9]+]]:gpr64 = SWPX [[CST]], [[COPY]] :: (load store monotonic 8 on %ir.addr)
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; CHECK: $x0 = COPY [[RES]]
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%0:gpr(p0) = COPY $x0
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%1:gpr(s64) = G_CONSTANT i64 1
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%2:gpr(s64) = G_ATOMICRMW_XCHG %0, %1 :: (load store monotonic 8 on %ir.addr)
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$x0 = COPY %2(s64)
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...
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---
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name: atomicrmw_add_i64
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: atomicrmw_add_i64
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; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK: [[CST:%[0-9]+]]:gpr64 = MOVi64imm 1
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; CHECK: [[RES:%[0-9]+]]:gpr64 = LDADDX [[CST]], [[COPY]] :: (load store monotonic 8 on %ir.addr)
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; CHECK: $x0 = COPY [[RES]]
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%0:gpr(p0) = COPY $x0
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%1:gpr(s64) = G_CONSTANT i64 1
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%2:gpr(s64) = G_ATOMICRMW_ADD %0, %1 :: (load store monotonic 8 on %ir.addr)
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$x0 = COPY %2(s64)
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...
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---
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name: atomicrmw_add_i32
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: atomicrmw_add_i32
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; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK: [[CST:%[0-9]+]]:gpr32 = MOVi32imm 1
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; CHECK: [[RES:%[0-9]+]]:gpr32 = LDADDALW [[CST]], [[COPY]] :: (load store seq_cst 8 on %ir.addr)
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; CHECK: $w0 = COPY [[RES]]
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%0:gpr(p0) = COPY $x0
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%1:gpr(s32) = G_CONSTANT i32 1
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%2:gpr(s32) = G_ATOMICRMW_ADD %0, %1 :: (load store seq_cst 8 on %ir.addr)
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$w0 = COPY %2(s32)
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...
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---
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name: atomicrmw_sub_i32
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: atomicrmw_sub_i32
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; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK: [[CST:%[0-9]+]]:gpr32 = MOVi32imm 1
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; CHECK: [[RES:%[0-9]+]]:gpr32 = LDADDALW [[CST]], [[COPY]] :: (load store seq_cst 8 on %ir.addr)
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; CHECK: $w0 = COPY [[RES]]
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%0:gpr(p0) = COPY $x0
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%1:gpr(s32) = G_CONSTANT i32 1
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%2:gpr(s32) = G_ATOMICRMW_ADD %0, %1 :: (load store seq_cst 8 on %ir.addr)
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$w0 = COPY %2(s32)
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...
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---
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name: atomicrmw_and_i32
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: atomicrmw_and_i32
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; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK: [[CST:%[0-9]+]]:gpr32 = MOVi32imm 1
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; CHECK: [[CST2:%[0-9]+]]:gpr32 = ORNWrr $wzr, [[CST]]
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; CHECK: [[RES:%[0-9]+]]:gpr32 = LDCLRAW [[CST2]], [[COPY]] :: (load store acquire 8 on %ir.addr)
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; CHECK: $w0 = COPY [[RES]]
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%0:gpr(p0) = COPY $x0
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%1:gpr(s32) = G_CONSTANT i32 1
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%2:gpr(s32) = G_ATOMICRMW_AND %0, %1 :: (load store acquire 8 on %ir.addr)
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$w0 = COPY %2(s32)
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...
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---
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name: atomicrmw_or_i32
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: atomicrmw_or_i32
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; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK: [[CST:%[0-9]+]]:gpr32 = MOVi32imm 1
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; CHECK: [[RES:%[0-9]+]]:gpr32 = LDSETLW [[CST]], [[COPY]] :: (load store release 8 on %ir.addr)
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; CHECK: $w0 = COPY [[RES]]
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%0:gpr(p0) = COPY $x0
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%1:gpr(s32) = G_CONSTANT i32 1
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%2:gpr(s32) = G_ATOMICRMW_OR %0, %1 :: (load store release 8 on %ir.addr)
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$w0 = COPY %2(s32)
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...
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---
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name: atomicrmw_xor_i32
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: atomicrmw_xor_i32
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; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK: [[CST:%[0-9]+]]:gpr32 = MOVi32imm 1
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; CHECK: [[RES:%[0-9]+]]:gpr32 = LDEORALW [[CST]], [[COPY]] :: (load store acq_rel 8 on %ir.addr)
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; CHECK: $w0 = COPY [[RES]]
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%0:gpr(p0) = COPY $x0
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%1:gpr(s32) = G_CONSTANT i32 1
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%2:gpr(s32) = G_ATOMICRMW_XOR %0, %1 :: (load store acq_rel 8 on %ir.addr)
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$w0 = COPY %2(s32)
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...
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---
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name: atomicrmw_min_i32
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: atomicrmw_min_i32
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; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK: [[CST:%[0-9]+]]:gpr32 = MOVi32imm 1
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; CHECK: [[RES:%[0-9]+]]:gpr32 = LDSMINALW [[CST]], [[COPY]] :: (load store acq_rel 8 on %ir.addr)
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; CHECK: $w0 = COPY [[RES]]
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%0:gpr(p0) = COPY $x0
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%1:gpr(s32) = G_CONSTANT i32 1
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%2:gpr(s32) = G_ATOMICRMW_MIN %0, %1 :: (load store acq_rel 8 on %ir.addr)
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$w0 = COPY %2(s32)
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...
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---
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name: atomicrmw_max_i32
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: atomicrmw_max_i32
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; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK: [[CST:%[0-9]+]]:gpr32 = MOVi32imm 1
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; CHECK: [[RES:%[0-9]+]]:gpr32 = LDSMAXALW [[CST]], [[COPY]] :: (load store acq_rel 8 on %ir.addr)
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; CHECK: $w0 = COPY [[RES]]
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%0:gpr(p0) = COPY $x0
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%1:gpr(s32) = G_CONSTANT i32 1
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%2:gpr(s32) = G_ATOMICRMW_MAX %0, %1 :: (load store acq_rel 8 on %ir.addr)
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$w0 = COPY %2(s32)
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...
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---
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name: atomicrmw_umin_i32
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: atomicrmw_umin_i32
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; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK: [[CST:%[0-9]+]]:gpr32 = MOVi32imm 1
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; CHECK: [[RES:%[0-9]+]]:gpr32 = LDUMINALW [[CST]], [[COPY]] :: (load store acq_rel 8 on %ir.addr)
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; CHECK: $w0 = COPY [[RES]]
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%0:gpr(p0) = COPY $x0
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%1:gpr(s32) = G_CONSTANT i32 1
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%2:gpr(s32) = G_ATOMICRMW_UMIN %0, %1 :: (load store acq_rel 8 on %ir.addr)
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$w0 = COPY %2(s32)
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...
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---
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name: atomicrmw_umax_i32
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: atomicrmw_umax_i32
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; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK: [[CST:%[0-9]+]]:gpr32 = MOVi32imm 1
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; CHECK: [[RES:%[0-9]+]]:gpr32 = LDUMAXALW [[CST]], [[COPY]] :: (load store acq_rel 8 on %ir.addr)
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; CHECK: $w0 = COPY [[RES]]
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%0:gpr(p0) = COPY $x0
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%1:gpr(s32) = G_CONSTANT i32 1
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%2:gpr(s32) = G_ATOMICRMW_UMAX %0, %1 :: (load store acq_rel 8 on %ir.addr)
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$w0 = COPY %2(s32)
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...
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