llvm-project/llvm/test/CodeGen
Heejin Ahn e0f8b9bfc6 [WebAssembly] Add null streamer support
Summary: Now `llc -filetype=null` works.

Reviewers: eush

Subscribers: dschuff, jgravelle-google, sbc100, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D54660

llvm-svn: 347155
2018-11-18 11:58:47 +00:00
..
AArch64 DAG combiner: fold (select, C, X, undef) -> X 2018-11-16 23:13:38 +00:00
AMDGPU Moved dag-combine-select-undef.ll into amdgpu. NFC. 2018-11-17 00:17:15 +00:00
ARC
ARM DAG combiner: fold (select, C, X, undef) -> X 2018-11-16 23:13:38 +00:00
AVR [AVR] Reorder the CHECK lines in directmem.ll to match current trunk 2018-11-09 23:17:59 +00:00
BPF [bpf] Test case for symbol information in object file 2018-09-22 17:31:01 +00:00
Generic Moved dag-combine-select-undef.ll into amdgpu. NFC. 2018-11-17 00:17:15 +00:00
Hexagon DAG combiner: fold (select, C, X, undef) -> X 2018-11-16 23:13:38 +00:00
Inputs
Lanai
MIR [Power9] Allow gpr callee saved spills in prologue to vectors registers 2018-11-09 16:36:24 +00:00
MSP430 [MSP430] Add RTLIB::[SRL/SRA/SHL]_I32 lowering to EABI lib calls 2018-11-16 19:36:15 +00:00
Mips [DAGCombiner][X86][Mips] Enable combineShuffleOfScalars to run between vector op legalization and DAG legalization. Fix bad one use check in combineShuffleOfScalars 2018-11-09 18:04:34 +00:00
NVPTX
Nios2
PowerPC [PowerPC][NFC] Add tests for vector fp <-> int conversions 2018-11-16 20:24:10 +00:00
RISCV [RISCV] Constant materialisation for RV64I 2018-11-16 10:14:16 +00:00
SPARC Relax fast register allocator related test cases; NFC 2018-10-29 20:10:42 +00:00
SystemZ DAG combiner: fold (select, C, X, undef) -> X 2018-11-16 23:13:38 +00:00
Thumb [SelectionDAG] swap select_cc operands to enable folding 2018-11-09 11:09:40 +00:00
Thumb2 [ARM] Enable spilling of the hGPR register class in Thumb2 2018-11-08 13:02:10 +00:00
WebAssembly [WebAssembly] Add null streamer support 2018-11-18 11:58:47 +00:00
WinCFGuard [COFF] Emit @feat.00 on 64-bit and set the CFG bit when emitting guardcf tables 2018-09-19 09:58:30 +00:00
WinEH
X86 [X86] Don't use a pmaddwd for vXi32 multiply if the inputs are zero extends from i8 or smaller without SSE4.1. Prefer to shrink the mul instead. 2018-11-18 05:53:21 +00:00
XCore Relax fast register allocator related test cases; NFC 2018-10-29 20:10:42 +00:00