forked from OSchip/llvm-project
116 lines
4.0 KiB
LLVM
116 lines
4.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --include-generated-funcs
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; RUN: opt -S -verify -iroutliner -ir-outlining-no-cost < %s | FileCheck %s
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; Check that differently ordered phi nodes are not matched when merged, instead
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; generating two output paths.
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define void @f1() {
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bb1:
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%0 = add i32 1, 2
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%1 = add i32 3, 4
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%2 = add i32 5, 6
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%3 = add i32 7, 8
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br i1 true, label %bb2, label %bb5
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bb2:
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%4 = mul i32 5, 4
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br label %bb5
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placeholder:
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%a = sub i32 5, 4
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ret void
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bb5:
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%phinode = phi i32 [%3, %bb1], [%2, %bb2]
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ret void
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}
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define void @f2() {
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bb1:
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%0 = add i32 1, 2
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%1 = add i32 3, 4
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%2 = add i32 5, 6
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%3 = add i32 7, 8
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br i1 true, label %bb2, label %bb5
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bb2:
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%4 = mul i32 5, 4
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br label %bb5
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placeholder:
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%a = sub i32 5, 4
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ret void
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bb5:
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%phinode = phi i32 [%2, %bb1], [%3, %bb2]
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ret void
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}
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; CHECK-LABEL: @f1(
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; CHECK-NEXT: bb1:
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; CHECK-NEXT: [[PHINODE_CE_LOC:%.*]] = alloca i32, align 4
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; CHECK-NEXT: [[LT_CAST:%.*]] = bitcast i32* [[PHINODE_CE_LOC]] to i8*
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; CHECK-NEXT: call void @llvm.lifetime.start.p0i8(i64 -1, i8* [[LT_CAST]])
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; CHECK-NEXT: [[TMP0:%.*]] = call i1 @outlined_ir_func_0(i32* [[PHINODE_CE_LOC]], i32 0)
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; CHECK-NEXT: [[PHINODE_CE_RELOAD:%.*]] = load i32, i32* [[PHINODE_CE_LOC]], align 4
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; CHECK-NEXT: call void @llvm.lifetime.end.p0i8(i64 -1, i8* [[LT_CAST]])
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; CHECK-NEXT: br i1 [[TMP0]], label [[BB5:%.*]], label [[BB1_AFTER_OUTLINE:%.*]]
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; CHECK: bb1_after_outline:
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; CHECK-NEXT: ret void
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; CHECK: bb5:
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; CHECK-NEXT: [[PHINODE:%.*]] = phi i32 [ [[PHINODE_CE_RELOAD]], [[BB1:%.*]] ]
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; CHECK-NEXT: ret void
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;
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;
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; CHECK-LABEL: @f2(
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; CHECK-NEXT: bb1:
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; CHECK-NEXT: [[PHINODE_CE_LOC:%.*]] = alloca i32, align 4
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; CHECK-NEXT: [[LT_CAST:%.*]] = bitcast i32* [[PHINODE_CE_LOC]] to i8*
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; CHECK-NEXT: call void @llvm.lifetime.start.p0i8(i64 -1, i8* [[LT_CAST]])
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; CHECK-NEXT: [[TMP0:%.*]] = call i1 @outlined_ir_func_0(i32* [[PHINODE_CE_LOC]], i32 1)
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; CHECK-NEXT: [[PHINODE_CE_RELOAD:%.*]] = load i32, i32* [[PHINODE_CE_LOC]], align 4
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; CHECK-NEXT: call void @llvm.lifetime.end.p0i8(i64 -1, i8* [[LT_CAST]])
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; CHECK-NEXT: br i1 [[TMP0]], label [[BB5:%.*]], label [[BB1_AFTER_OUTLINE:%.*]]
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; CHECK: bb1_after_outline:
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; CHECK-NEXT: ret void
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; CHECK: bb5:
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; CHECK-NEXT: [[PHINODE:%.*]] = phi i32 [ [[PHINODE_CE_RELOAD]], [[BB1:%.*]] ]
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; CHECK-NEXT: ret void
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;
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;
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; CHECK-LABEL: define internal i1 @outlined_ir_func_0(
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; CHECK-NEXT: newFuncRoot:
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; CHECK-NEXT: br label [[BB1_TO_OUTLINE:%.*]]
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; CHECK: bb1_to_outline:
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; CHECK-NEXT: [[TMP2:%.*]] = add i32 1, 2
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; CHECK-NEXT: [[TMP3:%.*]] = add i32 3, 4
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; CHECK-NEXT: [[TMP4:%.*]] = add i32 5, 6
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; CHECK-NEXT: [[TMP5:%.*]] = add i32 7, 8
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; CHECK-NEXT: br i1 true, label [[BB2:%.*]], label [[BB5_SPLIT:%.*]]
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; CHECK: bb2:
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; CHECK-NEXT: [[TMP6:%.*]] = mul i32 5, 4
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; CHECK-NEXT: br label [[BB5_SPLIT]]
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; CHECK: placeholder:
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; CHECK-NEXT: [[A:%.*]] = sub i32 5, 4
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; CHECK-NEXT: br label [[BB1_AFTER_OUTLINE_EXITSTUB:%.*]]
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; CHECK: bb5.split:
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; CHECK-NEXT: [[TMP7:%.*]] = phi i32 [ [[TMP4]], [[BB1_TO_OUTLINE]] ], [ [[TMP5]], [[BB2]] ]
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; CHECK-NEXT: [[PHINODE_CE:%.*]] = phi i32 [ [[TMP5]], [[BB1_TO_OUTLINE]] ], [ [[TMP4]], [[BB2]] ]
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; CHECK-NEXT: br label [[BB5_EXITSTUB:%.*]]
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; CHECK: bb5.exitStub:
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; CHECK-NEXT: switch i32 [[TMP1:%.*]], label [[FINAL_BLOCK_1:%.*]] [
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; CHECK-NEXT: i32 0, label [[OUTPUT_BLOCK_0_1:%.*]]
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; CHECK-NEXT: i32 1, label [[OUTPUT_BLOCK_1_1:%.*]]
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; CHECK-NEXT: ]
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; CHECK: bb1_after_outline.exitStub:
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; CHECK-NEXT: switch i32 [[TMP1]], label [[FINAL_BLOCK_0:%.*]] [
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; CHECK-NEXT: ]
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; CHECK: output_block_0_1:
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; CHECK-NEXT: store i32 [[PHINODE_CE]], i32* [[TMP0:%.*]], align 4
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; CHECK-NEXT: br label [[FINAL_BLOCK_1]]
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; CHECK: output_block_1_1:
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; CHECK-NEXT: store i32 [[TMP7]], i32* [[TMP0]], align 4
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; CHECK-NEXT: br label [[FINAL_BLOCK_1]]
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; CHECK: final_block_0:
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; CHECK-NEXT: ret i1 false
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; CHECK: final_block_1:
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; CHECK-NEXT: ret i1 true
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;
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