llvm-project/llvm/test/CodeGen/Hexagon/vect
Sanjay Patel 4b537aaf6d [DAGCombiner] allow narrowing of add followed by truncate
trunc (add X, C ) --> add (trunc X), C'

If we're throwing away the top bits of an 'add' instruction, do it in the narrow destination type.
This makes the truncate-able opcode list identical to the sibling transform done in IR (in instcombine).

This change used to show regressions for x86, but those are gone after D55494. 
This gets us closer to deleting the x86 custom function (combineTruncatedArithmetic) 
that does almost the same thing.

Differential Revision: https://reviews.llvm.org/D55866

llvm-svn: 350006
2018-12-22 17:10:31 +00:00
..
bit4x8.ll
build-vect64.ll
extract-elt-vNi1.ll
extract-v4i1.ll [Hexagon] Fix extracting subvectors of non-HVX vNi1 2018-10-02 15:05:43 +00:00
setcc-not.ll
setcc-v2i32.ll
setcc-v32.ll
shuff-32.ll
shuff-64.ll
vect-anyextend.ll
vect-apint-truncate.ll
vect-bad-bitcast.ll
vect-bitcast-1.ll
vect-bitcast.ll
vect-bool-basic-compile.ll
vect-bool-isel-crash.ll
vect-cst-v4i8.ll
vect-cst-v4i32.ll
vect-cst.ll
vect-extract-i1-debug.ll
vect-extract-i1.ll
vect-extract.ll
vect-fma.ll
vect-illegal-type.ll
vect-infloop.ll
vect-insert-extract-elt.ll
vect-load-1.ll
vect-load-v4i16.ll
vect-load.ll
vect-mul-v2i16.ll
vect-mul-v2i32.ll
vect-mul-v4i8.ll
vect-mul-v4i16.ll
vect-mul-v8i8.ll
vect-no-tfrs-1.ll
vect-no-tfrs.ll
vect-shift-imm.ll
vect-shuffle.ll
vect-splat.ll
vect-store-v2i16.ll
vect-truncate.ll
vect-v4i16.ll
vect-vaddb-1.ll
vect-vaddb.ll
vect-vaddh-1.ll
vect-vaddh.ll
vect-vaddw.ll
vect-vaslw.ll [DAGCombiner] allow narrowing of add followed by truncate 2018-12-22 17:10:31 +00:00
vect-vshifts.ll
vect-vsplatb.ll
vect-vsplath.ll
vect-vsubb-1.ll
vect-vsubb.ll
vect-vsubh-1.ll
vect-vsubh.ll
vect-vsubw.ll
vect-xor.ll
vect-zeroextend.ll
vsplat-v8i8.ll
zext-v4i1.ll