forked from OSchip/llvm-project
323 lines
16 KiB
TableGen
323 lines
16 KiB
TableGen
//===-- ARM.td - Describe the ARM Target Machine -----------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Target-independent interfaces which we are implementing
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//===----------------------------------------------------------------------===//
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include "llvm/Target/Target.td"
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//===----------------------------------------------------------------------===//
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// ARM Subtarget state.
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//
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def ModeThumb : SubtargetFeature<"thumb-mode", "InThumbMode", "true",
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"Thumb mode">;
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//===----------------------------------------------------------------------===//
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// ARM Subtarget features.
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//
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def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true",
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"Enable VFP2 instructions">;
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def FeatureVFP3 : SubtargetFeature<"vfp3", "HasVFPv3", "true",
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"Enable VFP3 instructions",
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[FeatureVFP2]>;
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def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
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"Enable NEON instructions",
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[FeatureVFP3]>;
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def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true",
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"Enable Thumb2 instructions">;
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def FeatureNoARM : SubtargetFeature<"noarm", "NoARM", "true",
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"Does not support ARM mode execution">;
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def FeatureFP16 : SubtargetFeature<"fp16", "HasFP16", "true",
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"Enable half-precision floating point">;
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def FeatureVFP4 : SubtargetFeature<"vfp4", "HasVFPv4", "true",
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"Enable VFP4 instructions",
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[FeatureVFP3, FeatureFP16]>;
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def FeatureD16 : SubtargetFeature<"d16", "HasD16", "true",
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"Restrict VFP3 to 16 double registers">;
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def FeatureHWDiv : SubtargetFeature<"hwdiv", "HasHardwareDivide", "true",
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"Enable divide instructions">;
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def FeatureHWDivARM : SubtargetFeature<"hwdiv-arm",
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"HasHardwareDivideInARM", "true",
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"Enable divide instructions in ARM mode">;
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def FeatureT2XtPk : SubtargetFeature<"t2xtpk", "HasT2ExtractPack", "true",
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"Enable Thumb2 extract and pack instructions">;
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def FeatureDB : SubtargetFeature<"db", "HasDataBarrier", "true",
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"Has data barrier (dmb / dsb) instructions">;
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def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true",
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"FP compare + branch is slow">;
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def FeatureVFPOnlySP : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true",
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"Floating point unit supports single precision only">;
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// Some processors have FP multiply-accumulate instructions that don't
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// play nicely with other VFP / NEON instructions, and it's generally better
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// to just not use them.
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def FeatureHasSlowFPVMLx : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true",
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"Disable VFP / NEON MAC instructions">;
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// Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding.
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def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding",
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"HasVMLxForwarding", "true",
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"Has multiplier accumulator forwarding">;
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// Some processors benefit from using NEON instructions for scalar
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// single-precision FP operations.
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def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP",
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"true",
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"Use NEON for single precision FP">;
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// Disable 32-bit to 16-bit narrowing for experimentation.
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def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true",
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"Prefer 32-bit Thumb instrs">;
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/// Some instructions update CPSR partially, which can add false dependency for
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/// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is
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/// mapped to a separate physical register. Avoid partial CPSR update for these
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/// processors.
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def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr",
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"AvoidCPSRPartialUpdate", "true",
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"Avoid CPSR partial update for OOO execution">;
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def FeatureAvoidMOVsShOp : SubtargetFeature<"avoid-movs-shop",
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"AvoidMOVsShifterOperand", "true",
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"Avoid movs instructions with shifter operand">;
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// Some processors perform return stack prediction. CodeGen should avoid issue
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// "normal" call instructions to callees which do not return.
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def FeatureHasRAS : SubtargetFeature<"ras", "HasRAS", "true",
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"Has return address stack">;
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/// Some M architectures don't have the DSP extension (v7E-M vs. v7M)
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def FeatureDSPThumb2 : SubtargetFeature<"t2dsp", "Thumb2DSP", "true",
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"Supports v7 DSP instructions in Thumb2">;
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// Multiprocessing extension.
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def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true",
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"Supports Multiprocessing extension">;
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// M-series ISA?
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def FeatureMClass : SubtargetFeature<"mclass", "IsMClass", "true",
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"Is microcontroller profile ('M' series)">;
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// Special TRAP encoding for NaCl, which looks like a TRAP in Thumb too.
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// See ARMInstrInfo.td for details.
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def FeatureNaClTrap : SubtargetFeature<"nacl-trap", "UseNaClTrap", "true",
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"NaCl trap">;
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// ARM ISAs.
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def HasV4TOps : SubtargetFeature<"v4t", "HasV4TOps", "true",
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"Support ARM v4T instructions">;
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def HasV5TOps : SubtargetFeature<"v5t", "HasV5TOps", "true",
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"Support ARM v5T instructions",
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[HasV4TOps]>;
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def HasV5TEOps : SubtargetFeature<"v5te", "HasV5TEOps", "true",
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"Support ARM v5TE, v5TEj, and v5TExp instructions",
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[HasV5TOps]>;
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def HasV6Ops : SubtargetFeature<"v6", "HasV6Ops", "true",
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"Support ARM v6 instructions",
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[HasV5TEOps]>;
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def HasV6T2Ops : SubtargetFeature<"v6t2", "HasV6T2Ops", "true",
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"Support ARM v6t2 instructions",
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[HasV6Ops, FeatureThumb2]>;
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def HasV7Ops : SubtargetFeature<"v7", "HasV7Ops", "true",
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"Support ARM v7 instructions",
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[HasV6T2Ops]>;
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//===----------------------------------------------------------------------===//
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// ARM Processors supported.
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//
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include "ARMSchedule.td"
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// ARM processor families.
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def ProcA5 : SubtargetFeature<"a5", "ARMProcFamily", "CortexA5",
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"Cortex-A5 ARM processors",
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[FeatureSlowFPBrcc, FeatureNEONForFP,
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FeatureHasSlowFPVMLx, FeatureVMLxForwarding,
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FeatureT2XtPk]>;
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def ProcA8 : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8",
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"Cortex-A8 ARM processors",
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[FeatureSlowFPBrcc, FeatureNEONForFP,
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FeatureHasSlowFPVMLx, FeatureVMLxForwarding,
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FeatureT2XtPk]>;
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def ProcA9 : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9",
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"Cortex-A9 ARM processors",
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[FeatureVMLxForwarding,
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FeatureT2XtPk, FeatureFP16,
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FeatureAvoidPartialCPSR]>;
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def ProcSwift : SubtargetFeature<"swift", "ARMProcFamily", "Swift",
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"Swift ARM processors",
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[FeatureNEONForFP, FeatureT2XtPk,
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FeatureVFP4, FeatureMP, FeatureHWDiv,
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FeatureHWDivARM, FeatureAvoidPartialCPSR,
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FeatureAvoidMOVsShOp,
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FeatureHasSlowFPVMLx]>;
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// FIXME: It has not been determined if A15 has these features.
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def ProcA15 : SubtargetFeature<"a15", "ARMProcFamily", "CortexA15",
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"Cortex-A15 ARM processors",
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[FeatureT2XtPk, FeatureFP16,
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FeatureAvoidPartialCPSR]>;
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def ProcR5 : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5",
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"Cortex-R5 ARM processors",
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[FeatureSlowFPBrcc, FeatureHWDivARM,
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FeatureHasSlowFPVMLx,
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FeatureAvoidPartialCPSR,
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FeatureT2XtPk]>;
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class ProcNoItin<string Name, list<SubtargetFeature> Features>
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: Processor<Name, NoItineraries, Features>;
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// V4 Processors.
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def : ProcNoItin<"generic", []>;
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def : ProcNoItin<"arm8", []>;
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def : ProcNoItin<"arm810", []>;
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def : ProcNoItin<"strongarm", []>;
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def : ProcNoItin<"strongarm110", []>;
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def : ProcNoItin<"strongarm1100", []>;
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def : ProcNoItin<"strongarm1110", []>;
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// V4T Processors.
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def : ProcNoItin<"arm7tdmi", [HasV4TOps]>;
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def : ProcNoItin<"arm7tdmi-s", [HasV4TOps]>;
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def : ProcNoItin<"arm710t", [HasV4TOps]>;
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def : ProcNoItin<"arm720t", [HasV4TOps]>;
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def : ProcNoItin<"arm9", [HasV4TOps]>;
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def : ProcNoItin<"arm9tdmi", [HasV4TOps]>;
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def : ProcNoItin<"arm920", [HasV4TOps]>;
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def : ProcNoItin<"arm920t", [HasV4TOps]>;
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def : ProcNoItin<"arm922t", [HasV4TOps]>;
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def : ProcNoItin<"arm940t", [HasV4TOps]>;
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def : ProcNoItin<"ep9312", [HasV4TOps]>;
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// V5T Processors.
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def : ProcNoItin<"arm10tdmi", [HasV5TOps]>;
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def : ProcNoItin<"arm1020t", [HasV5TOps]>;
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// V5TE Processors.
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def : ProcNoItin<"arm9e", [HasV5TEOps]>;
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def : ProcNoItin<"arm926ej-s", [HasV5TEOps]>;
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def : ProcNoItin<"arm946e-s", [HasV5TEOps]>;
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def : ProcNoItin<"arm966e-s", [HasV5TEOps]>;
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def : ProcNoItin<"arm968e-s", [HasV5TEOps]>;
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def : ProcNoItin<"arm10e", [HasV5TEOps]>;
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def : ProcNoItin<"arm1020e", [HasV5TEOps]>;
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def : ProcNoItin<"arm1022e", [HasV5TEOps]>;
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def : ProcNoItin<"xscale", [HasV5TEOps]>;
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def : ProcNoItin<"iwmmxt", [HasV5TEOps]>;
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// V6 Processors.
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def : Processor<"arm1136j-s", ARMV6Itineraries, [HasV6Ops]>;
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def : Processor<"arm1136jf-s", ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
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FeatureHasSlowFPVMLx]>;
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def : Processor<"arm1176jz-s", ARMV6Itineraries, [HasV6Ops]>;
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def : Processor<"arm1176jzf-s", ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
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FeatureHasSlowFPVMLx]>;
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def : Processor<"mpcorenovfp", ARMV6Itineraries, [HasV6Ops]>;
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def : Processor<"mpcore", ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
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FeatureHasSlowFPVMLx]>;
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// V6M Processors.
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def : Processor<"cortex-m0", ARMV6Itineraries, [HasV6Ops, FeatureNoARM,
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FeatureDB, FeatureMClass]>;
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// V6T2 Processors.
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def : Processor<"arm1156t2-s", ARMV6Itineraries, [HasV6T2Ops,
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FeatureDSPThumb2]>;
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def : Processor<"arm1156t2f-s", ARMV6Itineraries, [HasV6T2Ops, FeatureVFP2,
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FeatureHasSlowFPVMLx,
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FeatureDSPThumb2]>;
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// V7a Processors.
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// FIXME: A5 has currently the same Schedule model as A8
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def : ProcessorModel<"cortex-a5", CortexA8Model,
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[ProcA5, HasV7Ops, FeatureNEON, FeatureDB,
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FeatureVFP4, FeatureDSPThumb2,
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FeatureHasRAS]>;
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def : ProcessorModel<"cortex-a8", CortexA8Model,
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[ProcA8, HasV7Ops, FeatureNEON, FeatureDB,
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FeatureDSPThumb2, FeatureHasRAS]>;
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def : ProcessorModel<"cortex-a9", CortexA9Model,
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[ProcA9, HasV7Ops, FeatureNEON, FeatureDB,
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FeatureDSPThumb2, FeatureHasRAS]>;
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def : ProcessorModel<"cortex-a9-mp", CortexA9Model,
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[ProcA9, HasV7Ops, FeatureNEON, FeatureDB,
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FeatureDSPThumb2, FeatureMP,
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FeatureHasRAS]>;
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// FIXME: A15 has currently the same ProcessorModel as A9.
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def : ProcessorModel<"cortex-a15", CortexA9Model,
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[ProcA15, HasV7Ops, FeatureNEON, FeatureDB,
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FeatureDSPThumb2, FeatureHasRAS]>;
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// FIXME: R5 has currently the same ProcessorModel as A8.
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def : ProcessorModel<"cortex-r5", CortexA8Model,
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[ProcR5, HasV7Ops, FeatureDB,
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FeatureVFP3, FeatureDSPThumb2,
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FeatureHasRAS]>;
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// V7M Processors.
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def : ProcNoItin<"cortex-m3", [HasV7Ops,
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FeatureThumb2, FeatureNoARM, FeatureDB,
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FeatureHWDiv, FeatureMClass]>;
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// V7EM Processors.
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def : ProcNoItin<"cortex-m4", [HasV7Ops,
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FeatureThumb2, FeatureNoARM, FeatureDB,
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FeatureHWDiv, FeatureDSPThumb2,
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FeatureT2XtPk, FeatureVFP4,
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FeatureVFPOnlySP, FeatureMClass]>;
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// Swift uArch Processors.
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def : ProcessorModel<"swift", SwiftModel,
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[ProcSwift, HasV7Ops, FeatureNEON,
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FeatureDB, FeatureDSPThumb2,
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FeatureHasRAS]>;
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//===----------------------------------------------------------------------===//
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// Register File Description
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//===----------------------------------------------------------------------===//
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include "ARMRegisterInfo.td"
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include "ARMCallingConv.td"
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//===----------------------------------------------------------------------===//
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// Instruction Descriptions
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//===----------------------------------------------------------------------===//
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include "ARMInstrInfo.td"
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def ARMInstrInfo : InstrInfo;
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//===----------------------------------------------------------------------===//
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// Assembly printer
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//===----------------------------------------------------------------------===//
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// ARM Uses the MC printer for asm output, so make sure the TableGen
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// AsmWriter bits get associated with the correct class.
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def ARMAsmWriter : AsmWriter {
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string AsmWriterClassName = "InstPrinter";
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bit isMCAsmWriter = 1;
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}
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//===----------------------------------------------------------------------===//
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// Declare the target which we are implementing
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//===----------------------------------------------------------------------===//
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def ARM : Target {
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// Pull in Instruction Info:
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let InstructionSet = ARMInstrInfo;
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let AssemblyWriters = [ARMAsmWriter];
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}
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